print(t_test[0:5])
print(network.predict_int(x_test[0:5]))
network.params['W1'] = network.params['W1'] * 127.9
network.params['b1'] = network.params['b1'] * 16383.9
network.params['W2'] = network.params['W2'] * 127.9
network.params['b2'] = network.params['b2'] * 16383.9
network.params['W3'] = network.params['W3'] * 127.9
network.params['b3'] = network.params['b3'] * 16383.9
print(np.max(network.params['W1']))
print(np.min(network.params['W1']))
print(np.max(network.params['b1']))
print(np.min(network.params['b1']))
print(np.max(network.params['W2']))
print(np.min(network.params['W2']))
print(np.max(network.params['b2']))
print(np.min(network.params['b2']))
print(np.max(network.params['W3']))
print(np.min(network.params['W3']))
print(np.max(network.params['b3']))
print(np.min(network.params['b3']))
print(t_test[0:5])
x_test_rshft7 = x_test * 127.9
predict_result = network.predict(x_test_rshft7[0:5])/512
predict_result = np.int32(predict_result)
print(predict_result)
from __future__ import absolute_import
from __future__ import print_function
import sys
import os
import nngen as ng
# data types
act_dtype = ng.int32
weight_dtype = ng.int8
bias_dtype = ng.int8
scale_dtype = ng.int8
batchsize = 1
# input
input_layer = ng.placeholder(dtype=ng.int8,
shape=(batchsize, 28, 28, 1), # N, H, W, C
name='input_layer')
# layer 0: conv2d (with bias and scale (= batchnorm)), relu, max_pool
wn0 = ng.variable(dtype=weight_dtype,
shape=(10, 5, 5, 1), # Och, Ky, Kx, Ich
name='wn0')
bn0 = ng.variable(dtype=bias_dtype,
shape=(wn0.shape[0],), name='bn0')
sn0 = ng.variable(dtype=scale_dtype,
shape=(wn0.shape[0],), name='sn0')
a0 = ng.conv2d(input_layer, wn0,
strides=(1, 1, 1, 1),
bias=bn0,
scale=sn0,
padding='VALID',
act_func=ng.relu,
dtype=act_dtype,
sum_dtype=ng.int32)
a0p = ng.max_pool_serial(a0,
ksize=(1, 2, 2, 1),
strides=(1, 2, 2, 1))
a0r = ng.reshape(a0p, [batchsize, -1])
# layer 1: full-connection, relu
wn1 = ng.variable(weight_dtype,
shape=(100, a0r.shape[-1]),
name='wn1')
bn1 = ng.variable(bias_dtype,
shape=(wn1.shape[0],),
name='bn1')
sn1 = ng.variable(scale_dtype,
shape=(wn1.shape[0],),
name='sn1')
a1 = ng.matmul(a0r, wn1,
bias=bn1,
scale=sn1,
transposed_b=True,
act_func=ng.relu,
dtype=act_dtype,
sum_dtype=ng.int32)
# layer 2: full-connection, relu
wn2 = ng.variable(weight_dtype,
shape=(10, a1.shape[-1]),
name='wn2')
bn2 = ng.variable(bias_dtype,
shape=(wn2.shape[0],),
name='bn2')
sn2 = ng.variable(scale_dtype,
shape=(wn2.shape[0],),
name='sn2')
# output
output_layer = ng.matmul(a1, wn2,
bias=bn2,
scale=sn2,
transposed_b=True,
name='output_layer',
dtype=act_dtype,
sum_dtype=ng.int32)
wn0_value = W1n2.astype(np.int8)
wn0.set_value(wn0_value)
bn0_value = B1n2.astype(np.int8)
bn0.set_value(bn0_value)
sn0_value = np.ones(sn0.shape, dtype=np.int8)
sn0.set_value(sn0_value)
print(sn0_value[0])
wn1_value = W2n2.astype(np.int8)
wn1.set_value(wn1_value)
bn1_value = B2n2.astype(np.int8)
bn1.set_value(bn1_value)
sn1_value = np.ones(sn1.shape, dtype=np.int8)
sn1.set_value(sn1_value)
wn2_value = W3n2.astype(np.int8)
wn2.set_value(wn2_value)
bn2_value = B3n2.astype(np.int8)
bn2.set_value(bn2_value)
sn2_value = np.ones(sn2.shape, dtype=np.int8)
sn2.set_value(sn2_value)
# conv2d, matmul
# par_ich: parallelism in input-channel
# par_och: parallelism in output-channel
# par_col: parallelism in pixel column
# par_row: parallelism in pixel row
# cshamt_out: right shift amount after applying bias/scale
par_ich = 2
par_och = 2
cshamt_out = weight_dtype.width - 1
a0.attribute(par_ich=par_ich, par_och=par_och,
cshamt_out=0)
a1.attribute(par_ich=par_ich, par_och=par_och,
cshamt_out=0)
output_layer.attribute(par_ich=par_ich, par_och=par_och,
cshamt_out=weight_dtype.width +7)
# max_pool
# par: parallelism in in/out channel
par = par_och
a0p.attribute(par=par)
input_layer_value = x_test[0].reshape(input_layer.shape)
input_layer_value = input_layer_value * 127.9
input_layer_value = input_layer_value.astype(np.int8)
eval_outs = ng.eval([output_layer], input_layer=input_layer_value)
output_layer_value = eval_outs[0]
print(output_layer_value)
ということだったので、conv2d に”padding='VALID'”を追加した。padding='VALID'を指定するか、padding=0とすれば良いはずです
from __future__ import absolute_import
from __future__ import print_function
import sys
import os
import nngen as ng
# data types
act_dtype = ng.int8
weight_dtype = ng.int8
bias_dtype = ng.int8
scale_dtype = ng.int8
batchsize = 1
# input
input_layer = ng.placeholder(dtype=act_dtype,
shape=(batchsize, 28, 28, 1), # N, H, W, C
name='input_layer')
# layer 0: conv2d (with bias and scale (= batchnorm)), relu, max_pool
wn0 = ng.variable(dtype=weight_dtype,
shape=(10, 5, 5, 1), # Och, Ky, Kx, Ich
name='wn0')
bn0 = ng.variable(dtype=bias_dtype,
shape=(wn0.shape[0],), name='bn0')
sn0 = ng.variable(dtype=scale_dtype,
shape=(wn0.shape[0],), name='sn0')
a0 = ng.conv2d(input_layer, wn0,
strides=(1, 1, 1, 1),
bias=bn0,
scale=sn0,
padding='VALID',
act_func=ng.relu,
dtype=act_dtype,
sum_dtype=ng.int16)
a0p = ng.max_pool_serial(a0,
ksize=(1, 2, 2, 1),
strides=(1, 2, 2, 1))
a0r = ng.reshape(a0p, [batchsize, -1])
# layer 1: full-connection, relu
wn1 = ng.variable(weight_dtype,
shape=(100, a0r.shape[-1]),
name='wn1')
bn1 = ng.variable(bias_dtype,
shape=(wn1.shape[0],),
name='bn1')
sn1 = ng.variable(scale_dtype,
shape=(wn1.shape[0],),
name='sn1')
a1 = ng.matmul(a0r, wn1,
bias=bn1,
scale=sn1,
transposed_b=True,
act_func=ng.relu,
dtype=act_dtype,
sum_dtype=ng.int16)
# layer 2: full-connection, relu
wn2 = ng.variable(weight_dtype,
shape=(10, a1.shape[-1]),
name='wn2')
bn2 = ng.variable(bias_dtype,
shape=(wn2.shape[0],),
name='bn2')
sn2 = ng.variable(scale_dtype,
shape=(wn2.shape[0],),
name='sn2')
# output
output_layer = ng.matmul(a1, wn2,
bias=bn2,
scale=sn2,
transposed_b=True,
name='output_layer',
dtype=act_dtype,
sum_dtype=ng.int16)
print(wn0.shape)
print(bn0.shape)
print(wn1.shape)
print(bn1.shape)
print(wn2.shape)
print(bn2.shape)
print(a0.shape)
print(a0p.shape)
print(a0r.shape)
print(network.params['W1'].shape)
print(network.params['b1'].shape)
print(network.params['W2'].shape)
print(network.params['b2'].shape)
print(network.params['W3'].shape)
print(network.params['b3'].shape)
W1n = network.params['W1'].transpose(0,2,3,1)
print(W1n.shape)
print(np.max(W1n))
print(np.min(W1n))
B1n = network.params['b1']
print(np.max(B1n))
print(np.min(B1n))
W2n=network.params['W2'].transpose(1,0)
print(W2n.shape)
print(np.max(W2n))
print(np.min(W2n))
B2n = network.params['b2']
print(np.max(B2n))
print(np.min(B2n))
W3n=network.params['W3'].transpose(1,0)
print(W3n.shape)
print(np.max(W3n))
print(np.min(W3n))
B3n = network.params['b3']
print(np.max(B3n))
print(np.min(B3n))
AF_OUT_MAG = 2 ** 5 # 出力の小数部
AF_OUT_INT = 2 ** 11 # 出力の整数部(+符号1ビットされている)
AF_WB_MAG = 2 ** 7 # 重みとバイアスの小数部
AF_WB_INT = 2 ** 1 # 重みとバイアスの整数部(+符号1ビットされている)
COV_OUT_MAG = 2 ** 7 # 出力の小数部
COV_OUT_INT = 2 ** 9 # 出力の整数部(+符号1ビットされている)
COV_WB_MAG = 2 ** 7 # 重みとバイアスの小数部
COV_WB_INT = 2 ** 1 # 重みとバイアスの整数部(+符号1ビットされている)
0.16073333333333334 0.1679
0.90385 0.908
0.9256 0.9275
0.9395666666666667 0.9399
0.9454666666666667 0.9456
0.9488333333333333 0.9487
0.9575166666666667 0.955
0.9614833333333334 0.9589
0.9640333333333333 0.9614
0.9659833333333333 0.9606
0.9692 0.9624
0.9713333333333334 0.965
0.97315 0.9664
0.9748 0.9688
0.9768333333333333 0.9693
0.9778833333333333 0.969
0.9779666666666667 0.9704
(60000, 784)
np.max(x) = 1.0
np.min(x) = 0.0
(784, 50)
np.max(self.W) = 0.3671875
np.min(self.W) = -0.5625
(50,)
np.max(self.b) = 0.296875
np.min(self.b) = -0.171875
(60000, 50)
np.max(out) = 12.23468143302307
np.min(out) = -13.189215710841381
np.max(out2) = 12.234375
np.min(out2) = -13.1796875
(60000, 50)
np.max(x) = 12.234375
np.min(x) = 0.0
(50, 10)
np.max(self.W) = 0.9921875
np.min(self.W) = -1.0
(10,)
np.max(self.b) = 0.453125
np.min(self.b) = -0.3203125
(60000, 10)
np.max(out) = 29.58172607421875
np.min(out) = -25.99884033203125
np.max(out2) = 29.578125
np.min(out2) = -25.9921875
(10000, 784)
np.max(x) = 1.0
np.min(x) = 0.0
(784, 50)
np.max(self.W) = 0.3671875
np.min(self.W) = -0.5546875
(50,)
np.max(self.b) = 0.296875
np.min(self.b) = -0.1640625
(10000, 50)
np.max(out) = 12.447242664638907
np.min(out) = -10.870925284420082
np.max(out2) = 12.4453125
np.min(out2) = -10.859375
(10000, 50)
np.max(x) = 12.4453125
np.min(x) = 0.0
(50, 10)
np.max(self.W) = 0.9921875
np.min(self.W) = -0.9921875
(10,)
np.max(self.b) = 0.453125
np.min(self.b) = -0.3125
(10000, 10)
np.max(out) = 30.97119140625
np.min(out) = -24.920166015625
np.max(out2) = 30.96875
np.min(out2) = -24.9140625
0.9736166666666667 0.9559
from __future__ import absolute_import
from __future__ import print_function
import sys
import os
import nngen as ng
# data types
act_dtype = ng.int8
weight_dtype = ng.int8
bias_dtype = ng.int8
scale_dtype = ng.int16
# input
input_layer = ng.placeholder(dtype=act_dtype,
shape=(1, 28, 28, 1), # N, H, W, C
name='input_layer')
# layer 1: full-connection, relu
w_ng1 = ng.variable(weight_dtype,
shape=(784, input_layer.shape[-1]),
name='w_ng1')
b_ng1 = ng.variable(bias_dtype,
shape=(w_ng1.shape[0],),
name='b_ng1')
s_ng1 = ng.variable(scale_dtype,
shape=(w_ng1.shape[0],),
name='s_ng1')
a1 = ng.matmul(input_layer, w_ng1,
bias=b_ng1,
scale=s_ng1,
transposed_b=True,
act_func=ng.relu,
sum_dtype=ng.int16)
# layer 2: full-connection, relu
w_ng2 = ng.variable(weight_dtype,
shape=(10, a1.shape[-1]),
name='w_ng2')
b_ng2 = ng.variable(bias_dtype,
shape=(w_ng2.shape[0],),
name='b_ng2')
s_ng2 = ng.variable(scale_dtype,
shape=(w_ng2.shape[0],),
name='s_ng2')
# output
output_layer = ng.matmul(a1, w_ng2,
bias=b_ng2,
scale=s_ng2,
transposed_b=True,
name='output_layer',
sum_dtype=ng.int16)
MAGNIFICATION = 2 ** (9-1)
RANGE = 2 ** 4
0.08331666666666666 0.0837
0.9026166666666666 0.9077
0.9236 0.9253
0.9373833333333333 0.9383
0.9439666666666666 0.9411
0.9521 0.9493
0.9556 0.9509
0.9596666666666667 0.9539
0.96315 0.9583
0.9671666666666666 0.9605
0.9697833333333333 0.964
0.9716 0.9654
0.9730166666666666 0.9664
0.9749666666666666 0.9681
0.9768666666666667 0.9695
0.97805 0.9701
0.9791166666666666 0.9703
(60000, 784)
np.max(x) = 1.0
np.min(x) = 0.0
(784, 50)
np.max(self.W) = 0.421875
np.min(self.W) = -0.48046875
(50,)
np.max(self.b) = 0.296875
np.min(self.b) = -0.27734375
(60000, 50)
np.max(out) = 12.756525762986712
np.min(out) = -13.300428943461156
np.max(out2) = 12.7578125
np.min(out2) = -13.296875
(60000, 50)
np.max(x) = 12.7578125
np.min(x) = 0.0
(50, 10)
np.max(self.W) = 0.99609375
np.min(self.W) = -1.0
(10,)
np.max(self.b) = 0.34765625
np.min(self.b) = -0.375
(60000, 10)
np.max(out) = 27.193145751953125
np.min(out) = -24.312454223632812
np.max(out2) = 15.99609375
np.min(out2) = -16.0
(10000, 784)
np.max(x) = 1.0
np.min(x) = 0.0
(784, 50)
np.max(self.W) = 0.421875
np.min(self.W) = -0.4765625
(50,)
np.max(self.b) = 0.296875
np.min(self.b) = -0.2734375
(10000, 50)
np.max(out) = 14.379289269181754
np.min(out) = -11.566590114794963
np.max(out2) = 14.37890625
np.min(out2) = -11.5625
(10000, 50)
np.max(x) = 14.37890625
np.min(x) = 0.0
(50, 10)
np.max(self.W) = 0.99609375
np.min(self.W) = -0.99609375
(10,)
np.max(self.b) = 0.34765625
np.min(self.b) = -0.37109375
(10000, 10)
np.max(out) = 28.027145385742188
np.min(out) = -23.091751098632812
np.max(out2) = 15.99609375
np.min(out2) = -16.0
0.9781333333333333 0.9668
MAGNIFICATION = 2 ** (8-1)
RANGE = 2 ** 8
0.11151666666666667 0.1128
0.90435 0.9083
0.9233 0.925
0.9368333333333333 0.9332
0.9448333333333333 0.9407
0.9510666666666666 0.9485
0.9551833333333334 0.9515
0.9595166666666667 0.9569
0.9619333333333333 0.9578
0.96545 0.9604
0.9688833333333333 0.9634
0.9701333333333333 0.9635
0.97145 0.9639
0.9729166666666667 0.9662
0.97475 0.9672
0.9755 0.9668
0.9781333333333333 0.9687
(60000, 784)
np.max(x) = 1.0
np.min(x) = 0.0
(784, 50)
np.max(self.W) = 0.5
np.min(self.W) = -0.671875
(50,)
np.max(self.b) = 0.2890625
np.min(self.b) = -0.3046875
(60000, 50)
np.max(out) = 11.473192459365237
np.min(out) = -13.295526984147727
np.max(out2) = 11.4765625
np.min(out2) = -13.2890625
(60000, 50)
np.max(x) = 11.4765625
np.min(x) = 0.0
(50, 10)
np.max(self.W) = 0.9921875
np.min(self.W) = -1.0
(10,)
np.max(self.b) = 0.3828125
np.min(self.b) = -0.4296875
(60000, 10)
np.max(out) = 28.8548583984375
np.min(out) = -25.4957275390625
np.max(out2) = 28.8515625
np.min(out2) = -25.484375
(10000, 784)
np.max(x) = 1.0
np.min(x) = 0.0
(784, 50)
np.max(self.W) = 0.5
np.min(self.W) = -0.6640625
(50,)
np.max(self.b) = 0.2890625
np.min(self.b) = -0.296875
(10000, 50)
np.max(out) = 11.773253701612703
np.min(out) = -12.327052724038367
np.max(out2) = 11.7734375
np.min(out2) = -12.3203125
(10000, 50)
np.max(x) = 11.7734375
np.min(x) = 0.0
(50, 10)
np.max(self.W) = 0.9921875
np.min(self.W) = -0.9921875
(10,)
np.max(self.b) = 0.3828125
np.min(self.b) = -0.421875
(10000, 10)
np.max(out) = 30.44940185546875
np.min(out) = -26.7615966796875
np.max(out2) = 30.453125
np.min(out2) = -26.75
0.96955 0.947
PIC の SDI は ADXL355 の MISO に接続し、 SDO は ADXL355 の MOSI に接続している。後は同じ名前のピンを接続した。なお、PIC の SPI のピン配置はデフォルトの SPI ピンを使用している。SPI Master : SCLK - RC0(10 pin), SDI - RC1(9 pin), SDO - RC2(8 pin), /CS(GPIO) - RA2(11 pin)
/*
* File: acc3_uart.c
* Author: ono
*
* Created on 2021/02/03, 11:09
*/
// USART : RX - RC5(5 pin), TX - RC4(6 pin)(default)
// SPI Master : SCLK - RC0(10 pin), SDI - RC1(9 pin), SDO - RC2(8 pin), /CS(GPIO) - RA2(11 pin)
// acc_sensor : ADXL355
#include <xc.h>
#include <stdint.h>
#pragma config FOSC = INTOSC
//#pragma config WDTEN = OFF
#pragma config LVP = OFF
#pragma config PWRTE = ON
unsigned char chr;
unsigned int n = 0;
void Delay(unsigned int m)
{
for(n=0;n<m;n++); //Delay
}
void acc_sensor_write(uint8_t reg_addr, uint8_t write_data);
void acc_sensor_grecv(uint8_t dataX[3], uint8_t dataY[3], uint8_t dataZ[3]);
uint8_t acc_sensor_data_ready();
uint8_t acc_sensor_read_byte(uint8_t reg_addr);
void acc_sensor_read_3bytes(uint8_t reg_addr, uint8_t *data);
void main( void )
{
OSCCON = 0b11110000; // 4x PLL enable, 8MHz or 32MHz, FOSC
//OSCCON = 0b01111000; // 4x PLL disable, 16MHz, FOSC
OSCTUNE = 0x00;
TRISA = 0;
TRISC = 0x22; // SDI, UART RX is input setting.
ANSELA = 0;
ANSELC = 0;
// SPI
SSP1STAT = 0b11000000; // SMP=1, CKE=1
SSP1CON1 = 0b00100010; //SSP1EN=1, CKP=0, SPI Master, Clock=Fosc/64(500kHz)
SSP1CON3 = 0b00000000;
//SSP1IE = 1;
//SSP1IF = 0;
RA2 = 1; // SPI /CS = 1
// UART
BAUDCON = 0; // BRG16=0: 8bit counter mode
SPBRGL = 3; // SYNC=0, BRGH=1, BRG16=0, 500000bps
TXSTA = 0b00100100; // TXEN=1, SYNC=0, BRGH=1
RCSTA = 0b10010000; // SPEN=1, CREN=1
//INTCON = 0b11000000; // GIE=1, PEIE=1
RCIE = 1;
RCIF = 0;
PEIE = 1;
GIE = 1;
/*while(1){
while(TRMT == 0);
TXREG = 0x55;
Delay(50);
} */
uint8_t dataX[3], dataY[3], dataZ[3];
uint8_t count=0, count_b;
/*while(1){
acc_sensor_write(0x2c, 0x83); // I2C speed is Hi speed, +-8g
Delay(500);
}*/
acc_sensor_write(0x2c, 0x83); // I2C speed is Hi speed, +-8g
acc_sensor_write(0x1e, 0x00); // OFFSET_X_H
acc_sensor_write(0x1f, 0x00); // OFFSET_X_L
acc_sensor_write(0x20, 0x00); // OFFSET_Y_H
acc_sensor_write(0x21, 0x00); // OFFSET_Y_L
acc_sensor_write(0x22, 0x00); // OFFSET_Z_H
acc_sensor_write(0x23, 0x00); // OFFSET_Z_L
acc_sensor_write(0x2d, 0x00); // stanby clear
while(1){
while((acc_sensor_data_ready() & 0x01) == 0);
acc_sensor_read_3bytes(0x08, dataX);
//acc_sensor_grecv(dataX, dataY, dataZ);
Delay(500);
}
}
void interrupt RX_int(void){
if(RCIF == 1){
RCIF = 0;
chr = RCREG;
if(RCREG != 0x55)
return;
while(TRMT == 0);
TXREG = chr + 1;
}
}
void acc_sensor_write(uint8_t reg_addr, uint8_t write_data){
RA2 = 0; // SPI /CS = 0
SSP1IF = 0;
SSP1BUF = (reg_addr<<1);
while(SSP1IF == 0);
SSP1IF = 0;
SSP1BUF = write_data;
while(SSP1IF == 0);
RA2 = 1; // SPI /CS = 1
}
void acc_sensor_grecv(uint8_t *dataX, uint8_t *dataY, uint8_t *dataZ){
while((acc_sensor_data_ready() & 0x01) == 0);
acc_sensor_read_3bytes(0x08, dataX);
acc_sensor_read_3bytes(0x0b, dataY);
acc_sensor_read_3bytes(0x0e, dataZ);
}
uint8_t acc_sensor_data_ready(){
return(acc_sensor_read_byte(0x04));
}
uint8_t acc_sensor_read_byte(uint8_t reg_addr){
uint8_t data;
RA2 = 0; // SPI /CS = 0
SSP1IF = 0;
SSP1BUF = (reg_addr<<1) | 1;
while(SSP1IF == 0);
SSP1IF = 0;
SSP1BUF = 0;
while(SSP1IF == 0);
data = SSP1BUF;
RA2 = 1; // SPI /CS = 1
return(data);
}
void acc_sensor_read_3bytes(uint8_t reg_addr, uint8_t *data){
RA2 = 0; // SPI /CS = 0
SSP1IF = 0;
SSP1BUF = (reg_addr<<1) | 1;
while(SSP1IF == 0);
SSP1IF = 0;
SSP1BUF = 0;
while(SSP1IF == 0);
data[0] = SSP1BUF;
SSP1IF = 0;
SSP1BUF = 0;
while(SSP1IF == 0);
data[1] = SSP1BUF;
SSP1IF = 0;
SSP1BUF = 0;
while(SSP1IF == 0);
data[2] = SSP1BUF;
RA2 = 1; // SPI /CS = 1
}
masaaki@masaaki-H110M4-M01:/media/masaaki/Ubuntu_Disk/shtaxxx/nngen$ python3 hello_nngen.py
[[ 8 -18 3 -2 3 2 23 -8 0 -5]]
NNgen: Neural Network Accelerator Generator (version 1.3.1)
[IP-XACT]
Output: hello_nngen
[Configuration]
(AXI Master Interface)
Data width : 32
Address width: 32
(AXI Slave Interface)
Data width : 32
Address width: 32
[Schedule Table]
(Stage 0)
(Stage 1)
<conv2d None dtype:int8 shape:(1, 32, 32, 64) strides:(1, 1, 1, 1) padding:'SAME'-(1, 1, 1, 1) bias:(64,) scale:(64,) cshamt_out:17 act_func:relu sum_dtype:int32 par_ich:2 par_och:2 concur_och:16 stationary:filter keep_input default_addr:4242240 g_index:0 l_index:1 word_alignment:4 aligned_shape:(1, 32, 32, 64) scale_factor:2.625163>
| <placeholder input_layer dtype:int8 shape:(1, 32, 32, 3) default_addr:64 g_index:2 word_alignment:4 aligned_shape:(1, 32, 32, 4) scale_factor:64.000000>
| <variable w0 dtype:int8 shape:(64, 3, 3, 3) default_addr:4160 g_index:3 word_alignment:4 aligned_shape:(64, 3, 3, 4) scale_factor:42.333333>
| <variable b0 dtype:int32 shape:(64,) default_addr:4160 g_index:3 word_alignment:2 aligned_shape:(64,) scale_factor:2709.333333>
| <variable s0 dtype:int8 shape:(64,) default_addr:4160 g_index:3 word_alignment:4 aligned_shape:(64,) scale_factor:127.000000>
(Stage 2)
<max_pool_serial None dtype:int8 shape:(1, 16, 16, 64) ksize:(1, 2, 2, 1) strides:(1, 2, 2, 1) padding:'SAME'-(0, 0, 0, 0) par:2 no_reuse default_addr:4307776 g_index:0 l_index:2 word_alignment:4 aligned_shape:(1, 16, 16, 64) scale_factor:2.625163>
| <conv2d None dtype:int8 shape:(1, 32, 32, 64) strides:(1, 1, 1, 1) padding:'SAME'-(1, 1, 1, 1) bias:(64,) scale:(64,) cshamt_out:17 act_func:relu sum_dtype:int32 par_ich:2 par_och:2 concur_och:16 stationary:filter keep_input default_addr:4242240 g_index:0 l_index:1 word_alignment:4 aligned_shape:(1, 32, 32, 64) scale_factor:2.625163>
(Stage 3)
<conv2d None dtype:int8 shape:(1, 16, 16, 64) strides:(1, 1, 1, 1) padding:'SAME'-(1, 1, 1, 1) bias:(64,) scale:(64,) cshamt_out:16 act_func:relu sum_dtype:int32 par_ich:2 par_och:2 concur_och:16 stationary:filter default_addr:4324160 g_index:0 l_index:3 word_alignment:4 aligned_shape:(1, 16, 16, 64) scale_factor:0.215359>
| <max_pool_serial None dtype:int8 shape:(1, 16, 16, 64) ksize:(1, 2, 2, 1) strides:(1, 2, 2, 1) padding:'SAME'-(0, 0, 0, 0) par:2 no_reuse default_addr:4307776 g_index:0 l_index:2 word_alignment:4 aligned_shape:(1, 16, 16, 64) scale_factor:2.625163>
| <variable w1 dtype:int8 shape:(64, 3, 3, 64) default_addr:4160 g_index:3 word_alignment:4 aligned_shape:(64, 3, 3, 64) scale_factor:42.333333>
| <variable b1 dtype:int32 shape:(64,) default_addr:4160 g_index:3 word_alignment:2 aligned_shape:(64,) scale_factor:111.131890>
| <variable s1 dtype:int8 shape:(64,) default_addr:4160 g_index:3 word_alignment:4 aligned_shape:(64,) scale_factor:127.000000>
(Stage 4)
<_lazy_reshape None dtype:int8 shape:(1, 16384) alias_of:<conv2d> default_addr:4324160 g_index:0 l_index:3 word_alignment:4 aligned_shape:(1, 16384) scale_factor:0.215359>
| <conv2d None dtype:int8 shape:(1, 16, 16, 64) strides:(1, 1, 1, 1) padding:'SAME'-(1, 1, 1, 1) bias:(64,) scale:(64,) cshamt_out:16 act_func:relu sum_dtype:int32 par_ich:2 par_och:2 concur_och:16 stationary:filter default_addr:4324160 g_index:0 l_index:3 word_alignment:4 aligned_shape:(1, 16, 16, 64) scale_factor:0.215359>
(Stage 5)
<matmul None dtype:int8 shape:(1, 256) bias:(256,) scale:(256,) cshamt_out:19 act_func:relu sum_dtype:int32 par_left_col:2 par_out_col:2 concur_out_col:4 stationary:right keep_left default_addr:4340544 g_index:0 l_index:4 word_alignment:4 aligned_shape:(1, 256) scale_factor:0.002208>
| <_lazy_reshape None dtype:int8 shape:(1, 16384) alias_of:<conv2d> default_addr:4324160 g_index:0 l_index:3 word_alignment:4 aligned_shape:(1, 16384) scale_factor:0.215359>
| <variable w2 dtype:int8 shape:(256, 16384) default_addr:4160 g_index:3 word_alignment:4 aligned_shape:(256, 16384) scale_factor:42.333333>
| <variable b2 dtype:int32 shape:(256,) default_addr:4160 g_index:3 word_alignment:2 aligned_shape:(256,) scale_factor:9.116853>
| <variable s2 dtype:int8 shape:(256,) default_addr:4160 g_index:3 word_alignment:4 aligned_shape:(256,) scale_factor:127.000000>
(Stage 6)
<matmul output_layer dtype:int8 shape:(1, 10) bias:(10,) scale:(10,) cshamt_out:16 sum_dtype:int32 par_left_col:2 par_out_col:2 concur_out_col:256 stationary:right keep_left keep_right default_addr:0 g_index:1 word_alignment:4 aligned_shape:(1, 12) scale_factor:0.000181>
| <matmul None dtype:int8 shape:(1, 256) bias:(256,) scale:(256,) cshamt_out:19 act_func:relu sum_dtype:int32 par_left_col:2 par_out_col:2 concur_out_col:4 stationary:right keep_left default_addr:4340544 g_index:0 l_index:4 word_alignment:4 aligned_shape:(1, 256) scale_factor:0.002208>
| <variable w3 dtype:int8 shape:(10, 256) default_addr:4160 g_index:3 word_alignment:4 aligned_shape:(10, 256) scale_factor:42.333333>
| <variable b3 dtype:int32 shape:(10,) default_addr:4160 g_index:3 word_alignment:2 aligned_shape:(10,) scale_factor:0.093489>
| <variable s3 dtype:int8 shape:(10,) default_addr:4160 g_index:3 word_alignment:4 aligned_shape:(12,) scale_factor:127.000000>
[RAM (spec: num)]
64-bit 256-entry 2-port 1-bank RAM: 1
16-bit 32768-entry 2-port 2-bank RAM: 2
16-bit 8192-entry 2-port 2-bank RAM: 1
16-bit 512-entry 2-port 2-bank RAM: 31
[Substream (spec: num)]
('acc_rshift_round_frac', (32, 0, True, 32, 0, True)): 2
('add_tree', (32, 0, True, 2)): 2
('add_tree', (32, 0, True, 18)): 2
('mul_rshift_round_clip', (32, 0, True, 8, 0, True, 40, 0, True, 8, 0, True, False)): 2
('mul_rshift_round_madd', (8, 0, True, 8, 0, True, 16, 0, True)): 36
('reduce_max', (8, 0, True)): 2
[Stream (spec: num)]
(((<class 'nngen.operator.conv2d.conv2d'>, <dtype int8>, <dtype int8>, <dtype int32>, <dtype int8>), <dtype int8>, 1), 3, 3, False, None, <dtype int32>, 2, 2, 1, 1, 9, 36): 1
(((<class 'nngen.operator.pool_serial.max_pool_serial'>, <dtype int8>), <dtype int8>, 2), 2, 2, True, 2): 1
(((<class 'nngen.operator.basic._lazy_reshape'>, <dtype int8>), <dtype int8>, 1), True): 1
(((<class 'nngen.operator.matmul.matmul'>, <dtype int8>, <dtype int8>, <dtype int32>, <dtype int8>), <dtype int8>, 1), 1, 1, False, None, <dtype int32>, 2, 2, 1, 1, 1, 4): 1
[State IDs in main_fsm]
(3, 4, 'input_layer', 'None')
(12, 14, None, 'control_conv2d_4')
(18, 20, None, 'control_max_pool_serial_6')
(28, 30, None, 'control_conv2d_4')
(31, 32, None, 'None')
(40, 42, None, 'control_matmul_16')
(50, 52, 'output_layer', 'control_matmul_16')
[Control (name (# states: num))]
main_fsm (# states: 58)
control_conv2d_4 (# states: 56)
control_max_pool_serial_6 (# states: 26)
control_matmul_16 (# states: 41)
[Register Map]
0 (R ): header0 (default: 0x00000000)
4 (R ): header1 (default: 0x00000000)
8 (R ): header2 (default: 0x00000000)
12 (R ): header3 (default: 0x00000000)
16 ( W): Start (set '1' to run)
20 (R ): Busy (returns '1' when running)
24 ( W): Reset (set '1' to initialize internal logic)
28 (R ): Opcode from extern objects to SW (returns '0' when idle)
32 ( W): Resume extern objects (set '1' to resume)
36 (R ): Interrupt Status Register
40 ( W): Interrupt Enable Register
44 ( W): Interrupt Acknowledge Register
48 (R ): State Counter
52 ( W): Count Target
56 ( W): Count Divider
60 ( ): Reserved ...
120 ( ): ... Reserved
124 (R ): Address space amount
128 (RW): Global address offset (default: 0)
132 (RW): Address of temporal storages (size: 97KB)
136 (RW): Address of output (matmul) 'output_layer' (size: 64B, dtype: int8, shape: (1, 10), alignment: 4 words (4 bytes)), aligned shape: (1, 12)
140 (RW): Address of placeholder 'input_layer' (size: 4KB, dtype: int8, shape: (1, 32, 32, 3), alignment: 4 words (4 bytes)), aligned shape: (1, 32, 32, 4)
144 (RW): Address of variables 'w0', 'b0', 's0', 'w1', 'b1', 's1', 'w2', 'b2', 's2', 'w3', 'b3', 's3' (size: 4139KB)
[Default Memory Map (start - end)] (entire range: [0 - 4340799], size: 4240KB)
[ 0 - 63]: output (matmul) 'output_layer' (size: 64B, dtype: int8, shape: (1, 10), alignment: 4 words (4 bytes)), aligned shape: (1, 12)
[ 64 - 4159]: placeholder 'input_layer' (size: 4KB, dtype: int8, shape: (1, 32, 32, 3), alignment: 4 words (4 bytes)), aligned shape: (1, 32, 32, 4)
[ 4160 - 6463]: variable 'w0' (size: 3KB, dtype: int8, shape: (64, 3, 3, 3), alignment: 4 words (4 bytes)), aligned shape: (64, 3, 3, 4)
[ 6464 - 6719]: variable 'b0' (size: 256B, dtype: int32, shape: (64,), alignment: 2 words (8 bytes)), aligned shape: (64,)
[ 6720 - 6783]: variable 's0' (size: 64B, dtype: int8, shape: (64,), alignment: 4 words (4 bytes)), aligned shape: (64,)
[ 6784 - 43647]: variable 'w1' (size: 36KB, dtype: int8, shape: (64, 3, 3, 64), alignment: 4 words (4 bytes)), aligned shape: (64, 3, 3, 64)
[ 43648 - 43903]: variable 'b1' (size: 256B, dtype: int32, shape: (64,), alignment: 2 words (8 bytes)), aligned shape: (64,)
[ 43904 - 43967]: variable 's1' (size: 64B, dtype: int8, shape: (64,), alignment: 4 words (4 bytes)), aligned shape: (64,)
[ 43968 - 4238271]: variable 'w2' (size: 4096KB, dtype: int8, shape: (256, 16384), alignment: 4 words (4 bytes)), aligned shape: (256, 16384)
[4238272 - 4239295]: variable 'b2' (size: 1KB, dtype: int32, shape: (256,), alignment: 2 words (8 bytes)), aligned shape: (256,)
[4239296 - 4239551]: variable 's2' (size: 256B, dtype: int8, shape: (256,), alignment: 4 words (4 bytes)), aligned shape: (256,)
[4239552 - 4242111]: variable 'w3' (size: 3KB, dtype: int8, shape: (10, 256), alignment: 4 words (4 bytes)), aligned shape: (10, 256)
[4242112 - 4242175]: variable 'b3' (size: 64B, dtype: int32, shape: (10,), alignment: 2 words (8 bytes)), aligned shape: (10,)
[4242176 - 4242239]: variable 's3' (size: 64B, dtype: int8, shape: (10,), alignment: 4 words (4 bytes)), aligned shape: (12,)
[4242240 - 4340799]: temporal storages (size: 97KB)
# IP-XACT was generated. Check the current directory.
ar: Vout__ALL.a を作成しています
# start
# end
# execution cycles: 2993360
NG ( 0 0 ) orig: 10 check: 8
NG ( 0 1 ) orig: -19 check: -18
OK ( 0 2 ) orig: 3 check: 3
NG ( 0 3 ) orig: -1 check: -2
NG ( 0 4 ) orig: 4 check: 3
NG ( 0 5 ) orig: 3 check: 2
NG ( 0 6 ) orig: 24 check: 23
NG ( 0 7 ) orig: -9 check: -8
NG ( 0 8 ) orig: 1 check: 0
NG ( 0 9 ) orig: -4 check: -5
# verify: FAILED
- hello_nngen.out/out.v:1105: Verilog $finish
/*
* File: acc3_uart.c
* Author: ono
*
* Created on 2021/02/03, 11:09
*/
// "【PIC】I2C通信のやり方”のライブラリを引用している
// https://rikeden.net/?p=36
#include <xc.h>
#include <stdint.h>
#pragma config FOSC = INTOSC
//#pragma config WDTEN = OFF
#pragma config LVP = OFF
#pragma config PWRTE = ON
unsigned char chr;
unsigned int n = 0;
void Delay(unsigned int m)
{
for(n=0;n<m;n++); //Delay
}
void I2C_Master_Wait();
void I2C_Master_Start();
void I2C_Master_RepeatedStart();
void I2C_Master_Stop();
void I2C_Master_Write(uint8_t d);
uint8_t I2C_Master_Read(uint8_t a);
void acc_sensor_write(uint8_t dev_addr, uint8_t reg_addr, uint8_t write_data);
void acc_sensor_grecv(uint8_t dataX[3], uint8_t dataY[3], uint8_t dataZ[3]);
uint8_t acc_sensor_data_ready(uint8_t dev_addr);
uint8_t acc_sensor_read_byte(uint8_t dev_addr, uint8_t reg_addr);
void acc_sensor_read_3bytes(uint8_t dev_addr, uint8_t reg_addr, uint8_t *data);
void main( void )
{
OSCCON = 0b11110000; // 4x PLL enable, 8MHz or 32MHz, FOSC
OSCTUNE = 0x00;
TRISA = 0;
TRISC = 0x23; // SCL, SDA, UART RX is input setting.
ANSELA = 0;
ANSELC = 0;
//I2C
SSP1ADD = 19; //speed 400KHz
//SSP1ADD = 0x4F; //speed 100KHz
SSP1STAT = 0b10000000; // 400kHz
SSP1CON1 = 0b00101000; //SSP1EN=1, Master mode
SSP1CON2 = 0b00000000;
SSP1CON3 = 0b00000000;
//SSP1IE = 1;
//SSP1IF = 0;
// UART
BAUDCON = 0; // BRG16=0: 8bit counter mode
SPBRGL = 3; // SYNC=0, BRGH=1, BRG16=0, 500000bps
TXSTA = 0b00100100; // TXEN=1, SYNC=0, BRGH=1
RCSTA = 0b10010000; // SPEN=1, CREN=1
//INTCON = 0b11000000; // GIE=1, PEIE=1
RCIE = 1;
RCIF = 0;
PEIE = 1;
GIE = 1;
/*while(1){
while(TRMT == 0);
TXREG = 0x55;
Delay(50);
} */
uint8_t dataX[3], dataY[3], dataZ[3];
uint8_t count=0, count_b;
/*while(1){
acc_sensor_write(0x3a, 0x2c, 0x83); // I2C speed is Hi speed, +-8g
Delay(500);
}*/
acc_sensor_write(0x3a, 0x2c, 0x83); // I2C speed is Hi speed, +-8g
acc_sensor_write(0x3a, 0x1e, 0x00); // OFFSET_X_H
acc_sensor_write(0x3a, 0x1f, 0x00); // OFFSET_X_L
acc_sensor_write(0x3a, 0x20, 0x00); // OFFSET_Y_H
acc_sensor_write(0x3a, 0x21, 0x00); // OFFSET_Y_L
acc_sensor_write(0x3a, 0x22, 0x00); // OFFSET_Z_H
acc_sensor_write(0x3a, 0x23, 0x00); // OFFSET_Z_L
acc_sensor_write(0x3a, 0x2d, 0x00); // stanby clear
while(1){
while((acc_sensor_data_ready(0x3b) & 0x01) == 0);
//acc_sensor_read_3bytes(0x3b, 0x08, dataX);
acc_sensor_grecv(dataX, dataY, dataZ);
Delay(1000);
}
}
void interrupt RX_int(void){
if(RCIF == 1){
RCIF = 0;
chr = RCREG;
if(RCREG != 0x55)
return;
while(TRMT == 0);
TXREG = chr + 1;
}
}
void acc_sensor_write(uint8_t dev_addr, uint8_t reg_addr, uint8_t write_data){
I2C_Master_Start();
I2C_Master_Write(dev_addr);
I2C_Master_Write(reg_addr);
I2C_Master_Write(write_data);
I2C_Master_Stop();
}
void acc_sensor_grecv(uint8_t *dataX, uint8_t *dataY, uint8_t *dataZ){
while((acc_sensor_data_ready(0x3b) & 0x01) == 0);
acc_sensor_read_3bytes(0x3b, 0x08, dataX);
acc_sensor_read_3bytes(0x3b, 0x0b, dataY);
acc_sensor_read_3bytes(0x3b, 0x0e, dataZ);
}
uint8_t acc_sensor_data_ready(uint8_t dev_addr){
return(acc_sensor_read_byte(dev_addr, 0x04));
}
uint8_t acc_sensor_read_byte(uint8_t dev_addr, uint8_t reg_addr){
uint8_t data;
I2C_Master_Start();
I2C_Master_Write(dev_addr & 0xFE);
I2C_Master_Write(reg_addr);
I2C_Master_RepeatedStart();
I2C_Master_Write(dev_addr | 0x01);
data = I2C_Master_Read(1);
I2C_Master_Stop();
return(data);
}
void acc_sensor_read_3bytes(uint8_t dev_addr, uint8_t reg_addr, uint8_t *data){
I2C_Master_Start();
I2C_Master_Write(dev_addr & 0xFE);
I2C_Master_Write(reg_addr);
I2C_Master_RepeatedStart();
I2C_Master_Write(dev_addr | 0x01);
data[0] = I2C_Master_Read(0);
data[1] = I2C_Master_Read(0);
data[2] = I2C_Master_Read(1);
I2C_Master_Stop();
}
void I2C_Master_Wait(){
while ((SSP1STAT & 0x04) || (SSP1CON2 & 0x1F)); //Transmit is in progress
}
void I2C_Master_Start(){
I2C_Master_Wait();
SSP1CON2bits.SEN = 1; //Initiate start condition
}
void I2C_Master_RepeatedStart(){
I2C_Master_Wait();
SSP1CON2bits.RSEN = 1; //Initiate repeated start condition
}
void I2C_Master_Stop(){
I2C_Master_Wait();
SSP1CON2bits.PEN = 1; //Initiate stop condition
}
void I2C_Master_Write(uint8_t d){
I2C_Master_Wait();
SSP1BUF = d; //Write data to SSP1BUF
}
uint8_t I2C_Master_Read(uint8_t a){
uint8_t temp;
I2C_Master_Wait();
SSP1CON2bits.RCEN = 1;
I2C_Master_Wait();
temp = SSP1BUF; //Read data from SSP1BUF
I2C_Master_Wait();
SSP1CON2bits.ACKDT = a; //Acknowledge bit 1:NACK 0:ACK
SSP1CON2bits.ACKEN = 1; //Acknowledge sequence
return temp;
}
の 1 バイトの Read のトランザクションを示す。acc_sensor_read_byte(dev_addr, 0x04)
の 3 バイト Read トランザクションを示す。acc_sensor_read_3bytes(0x3b, 0x08, dataX);
/*
* File: acc3_uart.c
* Author: ono
*
* Created on 2021/02/03, 11:09
*/
#include <xc.h>
#include <stdint.h>
#pragma config FOSC = INTOSC
//#pragma config WDTEN = OFF
#pragma config LVP = OFF
#pragma config PWRTE = ON
unsigned char chr;
unsigned int n = 0;
uint8_t I2C_rw = 1; // 0 - Read, 1 - Write
#define I2C_READ 0
#define I2C_WRITE 1
uint8_t I2C_Read_bytes = 3; // 3 bytes or 1 byte
uint8_t I2C_WState = 0;
uint8_t I2C_RState = 0;
#define I2CW_IDLE 0
#define I2CW_SENT_START 1
#define I2CW_SENT_DEVICE_ADDR 2
#define I2CW_SENT_REG_ADDR 3
#define I2CW_SENT_DATA 4
#define I2CW_SENT_STOP 5
#define I2CR_IDLE 0
#define I2CR_SENT_START 1
#define I2CR_SENT_DEVICE_ADDR 2
#define I2CR_SENT_REG_ADDR 3
#define I2CR_SENT_REPEAT_START 4
#define I2CR_SENT_DEV_RADDR 5
#define I2CR_RECV_DATA0_WACK 6
#define I2CR_RECV_DATA0_WACK_DET 7
#define I2CR_RECV_DATA0_WNAK 8
#define I2CR_RECV_DATA1 9
#define I2CR_RECV_DATA1_WACK_DET 10
#define I2CR_RECV_DATA2_WNAK 11
#define I2CR_SEND_STOP 12
#define I2CR_SENT_STOP 13
uint8_t accs_dev_addr, accs_reg_addr, accs_write_data;
uint8_t accs_recv_data0, accs_recv_data1, accs_recv_data2;
void Delay(unsigned int m)
{
for(n=0;n<m;n++); //Delay
}
void acc_sensor_write(uint8_t dev_addr, uint8_t reg_addr, uint8_t write_data);
void acc_sensor_recv(uint8_t dataX[3], uint8_t dataY[3], uint8_t dataZ[3]);
void acc_sensor_recv_xyz(uint8_t dev_addr, uint8_t reg_addr, uint8_t data[3]);
void main( void )
{
OSCCON = 0b11110000; // 4x PLL enable, 8MHz or 32MHz, FOSC
OSCTUNE = 0x00;
TRISA = 0;
TRISC = 0x23; // SCL, SDA, UART RX is input setting.
ANSELA = 0;
ANSELC = 0;
//I2C
SSP1ADD = 19; //speed 400KHz
//SSP1ADD = 0x4F; //speed 100KHz
SSP1STAT = 0b10000000; // 400kHz
SSP1CON1 = 0b00101000; //SSP1EN=1, Master mode
SSP1CON2 = 0b00000000;
SSP1CON3 = 0b00000000;
SSP1IE = 1;
SSP1IF = 0;
// UART
BAUDCON = 0; // BRG16=0: 8bit counter mode
SPBRGL = 3; // SYNC=0, BRGH=1, BRG16=0, 500000bps
TXSTA = 0b00100100; // TXEN=1, SYNC=0, BRGH=1
RCSTA = 0b10010000; // SPEN=1, CREN=1
//INTCON = 0b11000000; // GIE=1, PEIE=1
RCIE = 1;
RCIF = 0;
PEIE = 1;
GIE = 1;
/*while(1){
while(TRMT == 0);
TXREG = 0x55;
Delay(50);
} */
uint8_t dataX[3], dataY[3], dataZ[3];
uint8_t count=0, count_b;
/*while(1){
acc_sensor_write(0x3a, 0x2c, 0x83); // I2C speed is Hi speed, +-8g
Delay(500);
}*/
acc_sensor_write(0x3a, 0x2c, 0x83); // I2C speed is Hi speed, +-8g
acc_sensor_write(0x3a, 0x1e, 0x00); // OFFSET_X_H
acc_sensor_write(0x3a, 0x1f, 0x00); // OFFSET_X_L
acc_sensor_write(0x3a, 0x20, 0x00); // OFFSET_Y_H
acc_sensor_write(0x3a, 0x21, 0x00); // OFFSET_Y_L
acc_sensor_write(0x3a, 0x22, 0x00); // OFFSET_Z_H
acc_sensor_write(0x3a, 0x23, 0x00); // OFFSET_Z_L
acc_sensor_write(0x3a, 0x2d, 0x00); // stanby clear
while(1){
acc_sensor_recv_xyz(0x3b, 0x08, dataX);
//acc_sensor_recv(dataX, dataY, dataZ);
Delay(100);
}
}
void interrupt RX_int(void){
if(RCIF == 1){
RCIF = 0;
chr = RCREG;
if(RCREG != 0x55)
return;
while(TRMT == 0);
TXREG = chr + 1;
} else if(SSP1IF == 1){
if(I2C_rw == I2C_WRITE){
switch(I2C_WState){
case I2CW_SENT_START:
SSP1IF = 0;
SSP1BUF = accs_dev_addr & 0xFE; // dev_addr to SSP1BUF for Write
I2C_WState = I2CW_SENT_DEVICE_ADDR;
break;
case I2CW_SENT_DEVICE_ADDR:
SSP1IF = 0;
SSP1BUF = accs_reg_addr; // reg_addr to SSP1BUF
I2C_WState = I2CW_SENT_REG_ADDR;
break;
case I2CW_SENT_REG_ADDR:
SSP1IF = 0;
SSP1BUF = accs_write_data; // write_data to SSP1BUF
I2C_WState = I2CW_SENT_DATA;
break;
case I2CW_SENT_DATA:
SSP1IF = 0;
SSP1CON2bits.PEN = 1; //Initiate stop condition
I2C_WState = I2CW_SENT_STOP;
break;
case I2CW_SENT_STOP:
SSP1IF = 0;
I2C_WState = I2CW_IDLE;
break;
default:
break;
}
} else { // I2C_rw == I2C_READ;
switch(I2C_RState){
case I2CR_SENT_START:
SSP1IF = 0;
SSP1BUF = accs_dev_addr & 0xFE; // dev_addr to SSP1BUF for Write
I2C_RState = I2CR_SENT_DEVICE_ADDR;
break;
case I2CR_SENT_DEVICE_ADDR:
SSP1IF = 0;
SSP1BUF = accs_reg_addr; // reg_addr to SSP1BUF
I2C_RState = I2CR_SENT_REG_ADDR;
break;
case I2CR_SENT_REG_ADDR:
SSP1IF = 0;
SSP1CON2bits.RSEN = 1; // Repeat Star
I2C_RState = I2CR_SENT_REPEAT_START;
break;
case I2CR_SENT_REPEAT_START:
SSP1IF = 0;
SSP1BUF = accs_dev_addr | 1; // dev_addr to SSP1BUF for Read
I2C_RState = I2CR_SENT_DEV_RADDR;
break;
case I2CR_SENT_DEV_RADDR:
SSP1IF = 0;
SSP1CON2bits.RCEN = 1; // Recieve Enable
if(I2C_Read_bytes == 3)
I2C_RState = I2CR_RECV_DATA0_WACK;
else
I2C_RState = I2CR_RECV_DATA0_WNAK;
break;
case I2CR_RECV_DATA0_WNAK:
SSP1IF = 0;
SSP1CON2bits.ACKDT = 1; // NACK
SSP1CON2bits.ACKEN = 1;
accs_recv_data0 = SSP1BUF; //Read data from SSP1BUF
I2C_RState = I2CR_SEND_STOP;
break;
case I2CR_RECV_DATA0_WACK:
SSP1IF = 0;
SSP1CON2bits.ACKDT = 0; // ACK
SSP1CON2bits.ACKEN = 1;
accs_recv_data0 = SSP1BUF; //Read data from SSP1BUF
I2C_RState = I2CR_RECV_DATA0_WACK_DET;
break;
case I2CR_RECV_DATA0_WACK_DET:
SSP1IF = 0;
SSP1CON2bits.RCEN = 1; // Recieve Enable
I2C_RState = I2CR_RECV_DATA1;
break;
case I2CR_RECV_DATA1:
SSP1IF = 0;
SSP1CON2bits.ACKDT = 0; // ACK
SSP1CON2bits.ACKEN = 1;
accs_recv_data1 = SSP1BUF; //Read data from SSP1BUF
I2C_RState = I2CR_RECV_DATA1_WACK_DET;
break;
case I2CR_RECV_DATA1_WACK_DET:
SSP1IF = 0;
SSP1CON2bits.RCEN = 1; // Recieve Enable
I2C_RState = I2CR_RECV_DATA2_WNAK;
break;
case I2CR_RECV_DATA2_WNAK:
SSP1IF = 0;
SSP1CON2bits.ACKDT = 1; // NACK
SSP1CON2bits.ACKEN = 1;
accs_recv_data2 = SSP1BUF; //Read data from SSP1BUF
I2C_RState = I2CR_SEND_STOP;
break;
case I2CR_SEND_STOP:
SSP1IF = 0;
SSP1CON2bits.PEN = 1; //Initiate stop condition
I2C_RState = I2CR_SENT_STOP;
break;
case I2CR_SENT_STOP:
SSP1IF = 0;
I2C_RState = I2CR_IDLE;
break;
default:
break;
}
}
}
}
void acc_sensor_write(uint8_t dev_addr, uint8_t reg_addr, uint8_t write_data){
while(I2C_WState != I2CW_IDLE);
while(I2C_RState != I2CR_IDLE);
accs_dev_addr = dev_addr;
accs_reg_addr = reg_addr;
accs_write_data = write_data;
I2C_rw = I2C_WRITE;
I2C_WState = I2CW_SENT_START;
SSP1CON2bits.SEN = 1; //Initiate start condition
while(I2C_WState != I2CW_IDLE); // Wait I2C Write
//Delay(10);
}
void acc_sensor_recv(uint8_t *dataX, uint8_t *dataY, uint8_t *dataZ){
acc_sensor_recv_xyz(0x3b, 0x08, dataX);
acc_sensor_recv_xyz(0x3b, 0x0b, dataY);
acc_sensor_recv_xyz(0x3b, 0x0e, dataZ);
}
void acc_sensor_recv_xyz(uint8_t dev_addr, uint8_t reg_addr, uint8_t *data){
while(I2C_WState != I2CW_IDLE);
while(I2C_RState != I2CR_IDLE);
do{ // Wait data ready
accs_dev_addr = 0x3b;
accs_reg_addr = 0x04; // Watch data ready
I2C_rw = I2C_READ;
I2C_RState = I2CR_SENT_START;
I2C_Read_bytes = 1; // 3 bytes or 1 byte
SSP1CON2bits.SEN = 1; //Initiate start condition
while(I2C_RState != I2CR_IDLE); // Wait I2C Read
}while((accs_recv_data0 & 0x01) != 0x01);
//Delay(10);
accs_dev_addr = dev_addr;
accs_reg_addr = reg_addr;
I2C_rw = I2C_READ;
I2C_RState = I2CR_SENT_START;
I2C_Read_bytes = 3; // 3 bytes or 1 byte
SSP1CON2bits.SEN = 1; //Initiate start condition
while(I2C_RState != I2CR_IDLE); // Wait I2C Read
data[0] = accs_recv_data0;
data[1] = accs_recv_data1;
data[2] = accs_recv_data2;
//Delay(10);
}
の波形を示す。acc_sensor_write(0x3a, 0x2c, 0x83); // I2C speed is Hi speed, +-8g
を入力した。_SLXLoopInterchange();
コマンドラインおよび Vitis HLS IDEからSLXプラグインループ交換最適化を使用する方法。ローカルのLLVMビルドは必要ありません。
-include /media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/slxplugin_loopinterchange_demo/slxplugin/include/slxplugin.h
masaaki@masaaki-H110M4-M01:/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/slxplugin_loopinterchange_demo$ vitis_hls run_hls.tcl
****** Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit)
**** SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
**** IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020
** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
source /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis_HLS/2020.2/scripts/vitis_hls/hls.tcl -notrace
Sourcing tcl script 'scripts/vitis_hls_init.tcl'
slxplugin=/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/slxplugin_loopinterchange_demo/slxplugin
INFO: [HLS 200-10] Running '/media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis_HLS/2020.2/bin/unwrapped/lnx64.o/vitis_hls'
INFO: [HLS 200-10] For user 'masaaki' on host 'masaaki-H110M4-M01' (Linux_x86_64 version 4.15.0-136-generic) on Mon Mar 15 19:51:38 JST 2021
INFO: [HLS 200-10] On os Ubuntu 18.04.5 LTS
INFO: [HLS 200-10] In directory '/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/slxplugin_loopinterchange_demo'
WARNING: [HLS 200-40] Environment variable 'C_INCLUDE_PATH' is set to :/usr/local/cuda/include.
Sourcing Tcl script 'run_hls.tcl'
INFO: [HLS 200-1510] Running: ::xilinx_open_project -reset proj
INFO: [HLS 200-10] Creating and opening project '/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/slxplugin_loopinterchange_demo/proj'.
INFO: [HLS 200-1510] Running: add_files code.cpp -cflags -include /media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/slxplugin_loopinterchange_demo/slxplugin/include/slxplugin.h
INFO: [HLS 200-10] Adding design file 'code.cpp' to the project
INFO: [HLS 200-1510] Running: add_files -tb code_test.cpp
INFO: [HLS 200-10] Adding test bench file 'code_test.cpp' to the project
INFO: [HLS 200-1510] Running: set_top reduce_2d_to_1d
SOLUTION 0.vanilla: no LLVM_CUSTOM_CMD, no Xilinx directives (clock: 333MHz)
INFO: [HLS 200-1510] Running: open_solution -reset 0.vanilla
INFO: [HLS 200-10] Creating and opening solution '/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/slxplugin_loopinterchange_demo/proj/0.vanilla'.
INFO: [HLS 200-10] Cleaning up the solution database.
WARNING: [HLS 200-40] No /media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/slxplugin_loopinterchange_demo/proj/0.vanilla/0.vanilla.aps file found.
INFO: [HLS 200-1505] Using default flow_target 'vivado'
Resolution: For help on HLS 200-1505 see www.xilinx.com/cgi-bin/docs/rdoc?v=2020.2;t=hls+guidance;d=200-1505.html
INFO: [HLS 200-1510] Running: set_part xcvu9p-flga2104-2-i
INFO: [HLS 200-10] Setting target device to 'xcvu9p-flga2104-2-i'
INFO: [HLS 200-1510] Running: create_clock -period 333MHz
INFO: [SYN 201-201] Setting up clock 'default' with a period of 3.003ns.
INFO: [HLS 200-1510] Running: csim_design
INFO: [SIM 211-2] *************** CSIM start ***************
INFO: [SIM 211-4] CSIM will launch GCC as the compiler.
Compiling ../../../../code_test.cpp in debug mode
Compiling ../../../../code.cpp in debug mode
Generating csim.exe
58240
123777
189314
254851
320388
385925
451462
516999
582536
648073
713610
779147
844684
910221
975758
1.0413e+06
1.10683e+06
1.17237e+06
1.23791e+06
1.30344e+06
1.36898e+06
1.43452e+06
1.50005e+06
1.56559e+06
1.63113e+06
1.69666e+06
1.7622e+06
1.82774e+06
1.89328e+06
1.95881e+06
2.02435e+06
2.08989e+06
2.15542e+06
2.22096e+06
2.2865e+06
2.35204e+06
2.41757e+06
2.48311e+06
2.54865e+06
2.61418e+06
2.67972e+06
2.74526e+06
2.81079e+06
2.87633e+06
2.94187e+06
3.0074e+06
3.07294e+06
3.13848e+06
3.20402e+06
3.26955e+06
3.33509e+06
3.40063e+06
3.46616e+06
3.5317e+06
3.59724e+06
3.66278e+06
3.72831e+06
3.79385e+06
3.85939e+06
3.92492e+06
3.99046e+06
4.056e+06
4.12153e+06
4.18707e+06
4.25261e+06
4.31814e+06
4.38368e+06
4.44922e+06
4.51476e+06
4.58029e+06
4.64583e+06
4.71137e+06
4.7769e+06
4.84244e+06
4.90798e+06
4.97352e+06
5.03905e+06
5.10459e+06
5.17013e+06
5.23566e+06
5.3012e+06
5.36674e+06
5.43227e+06
5.49781e+06
5.56335e+06
5.62888e+06
5.69442e+06
5.75996e+06
5.8255e+06
5.89103e+06
5.95657e+06
6.02211e+06
6.08764e+06
6.15318e+06
6.21872e+06
6.28426e+06
6.34979e+06
6.41533e+06
6.48087e+06
6.5464e+06
6.61194e+06
6.67748e+06
6.74301e+06
6.80855e+06
6.87409e+06
6.93962e+06
7.00516e+06
7.0707e+06
7.13624e+06
7.20177e+06
7.26731e+06
7.33285e+06
7.39838e+06
7.46392e+06
7.52946e+06
7.595e+06
7.66053e+06
7.72607e+06
7.79161e+06
7.85714e+06
7.92268e+06
7.98822e+06
8.05375e+06
8.11929e+06
8.18483e+06
8.25036e+06
8.3159e+06
8.38144e+06
8.44698e+06
8.51251e+06
8.57805e+06
8.64359e+06
8.70912e+06
8.77466e+06
8.8402e+06
8.90574e+06
8.97127e+06
9.03681e+06
9.10235e+06
9.16788e+06
9.23342e+06
9.29896e+06
9.36449e+06
9.43003e+06
9.49557e+06
9.5611e+06
9.62664e+06
9.69218e+06
9.75772e+06
9.82325e+06
9.88879e+06
9.95433e+06
1.00199e+07
1.00854e+07
1.01509e+07
1.02165e+07
1.0282e+07
1.03475e+07
1.04131e+07
1.04786e+07
1.05442e+07
1.06097e+07
1.06752e+07
1.07408e+07
1.08063e+07
1.08718e+07
1.09374e+07
1.10029e+07
1.10685e+07
1.1134e+07
1.11995e+07
1.12651e+07
1.13306e+07
1.13961e+07
1.14617e+07
1.15272e+07
1.15928e+07
1.16583e+07
1.17238e+07
1.17894e+07
1.18549e+07
1.19204e+07
1.1986e+07
1.20515e+07
1.2117e+07
1.21826e+07
1.22481e+07
1.23137e+07
1.23792e+07
1.24447e+07
1.25103e+07
1.25758e+07
1.26413e+07
1.27069e+07
1.27724e+07
1.2838e+07
1.29035e+07
1.2969e+07
1.30346e+07
1.31001e+07
1.31656e+07
1.32312e+07
1.32967e+07
1.33623e+07
1.34278e+07
1.34933e+07
1.35589e+07
1.36244e+07
1.36899e+07
1.37555e+07
1.3821e+07
1.38865e+07
1.39521e+07
1.40176e+07
1.40832e+07
1.41487e+07
1.42142e+07
1.42798e+07
1.43453e+07
1.44108e+07
1.44764e+07
1.45419e+07
1.46075e+07
1.4673e+07
1.47385e+07
1.48041e+07
1.48696e+07
1.49351e+07
1.50007e+07
1.50662e+07
1.51318e+07
1.51973e+07
1.52628e+07
1.53284e+07
1.53939e+07
1.54594e+07
1.5525e+07
1.55905e+07
1.5656e+07
1.57216e+07
1.57871e+07
1.58527e+07
1.59182e+07
1.59837e+07
1.60493e+07
1.61148e+07
1.61803e+07
1.62459e+07
1.63114e+07
1.6377e+07
1.64425e+07
1.6508e+07
1.65736e+07
1.66391e+07
1.67046e+07
1.67702e+07
check successful
INFO: [SIM 211-1] CSim done with 0 errors.
INFO: [SIM 211-3] *************** CSIM finish ***************
INFO: [HLS 200-111] Finished Command csim_design CPU user time: 1.15 seconds. CPU system time: 0.24 seconds. Elapsed time: 0.88 seconds; current allocated memory: 163.205 MB.
INFO: [HLS 200-1510] Running: ::xilinx_csynth_design
INFO: [HLS 200-111] Finished File checks and directory preparation: CPU user time: 0 seconds. CPU system time: 0 seconds. Elapsed time: 0 seconds; current allocated memory: 163.387 MB.
INFO: [HLS 200-10] Analyzing design file 'code.cpp' ...
INFO: [HLS 200-111] Finished Source Code Analysis and Preprocessing: CPU user time: 0.1 seconds. CPU system time: 0.09 seconds. Elapsed time: 0.2 seconds; current allocated memory: 164.058 MB.
INFO: [HLS 200-1022] Execute customized passes: $LLVM_CUSTOM_OPT -load /media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/slxplugin_loopinterchange_demo/slxplugin/lib/slxplugin.so -slx-remove-directives $LLVM_CUSTOM_INPUT -o $LLVM_CUSTOM_OUTPUT
LLVM_CUSTOM_OPT:/media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis_HLS/2020.2/lnx64/tools/clang-3.9-csynth/bin/opt
LLVM_CUSTOM_INPUT:/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/slxplugin_loopinterchange_demo/proj/0.vanilla/.autopilot/db/a.g.ld.5.gdce.bc
LLVM_CUSTOM_OUTPUT:/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/slxplugin_loopinterchange_demo/proj/0.vanilla/.autopilot/db/a.g.ld.6.user.bc
INFO: [HLS 200-777] Using interface defaults for 'Vivado' flow target.
INFO: [HLS 200-111] Finished Compiling Optimization and Transform: CPU user time: 3.38 seconds. CPU system time: 0.26 seconds. Elapsed time: 3.63 seconds; current allocated memory: 165.969 MB.
INFO: [HLS 200-111] Finished Checking Pragmas: CPU user time: 0 seconds. CPU system time: 0 seconds. Elapsed time: 0 seconds; current allocated memory: 165.969 MB.
INFO: [HLS 200-10] Starting code transformations ...
INFO: [HLS 200-111] Finished Standard Transforms: CPU user time: 0.01 seconds. CPU system time: 0 seconds. Elapsed time: 0.01 seconds; current allocated memory: 167.159 MB.
INFO: [HLS 200-10] Checking synthesizability ...
INFO: [HLS 200-111] Finished Checking Synthesizability: CPU user time: 0.01 seconds. CPU system time: 0 seconds. Elapsed time: 0.02 seconds; current allocated memory: 166.371 MB.
INFO: [XFORM 203-510] Pipelining loop 'loop_in' (code.cpp:15) in function 'reduce_2d_to_1d' automatically.
INFO: [HLS 200-111] Finished Loop, function and other optimizations: CPU user time: 0.05 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.05 seconds; current allocated memory: 186.787 MB.
WARNING: [HLS 200-960] Cannot flatten loop 'loop_out' (code.cpp:14:21) in function 'reduce_2d_to_1d' the outer loop is not a perfect loop.
Resolution: For help on HLS 200-960 see www.xilinx.com/cgi-bin/docs/rdoc?v=2020.2;t=hls+guidance;d=200-960.html
INFO: [HLS 200-111] Finished Architecture Synthesis: CPU user time: 0.04 seconds. CPU system time: 0 seconds. Elapsed time: 0.03 seconds; current allocated memory: 179.068 MB.
INFO: [HLS 200-10] Starting hardware synthesis ...
INFO: [HLS 200-10] Synthesizing 'reduce_2d_to_1d' ...
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-42] -- Implementing module 'reduce_2d_to_1d'
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [SCHED 204-11] Starting scheduling ...
INFO: [SCHED 204-61] Pipelining loop 'loop_in'.
WARNING: [HLS 200-881] Unable to enforce a carried constraint (II = 1) between 'dadd' operation ('add', code.cpp:17) and 'dadd' operation ('add', code.cpp:17).
Resolution: For help on HLS 200-881 see www.xilinx.com/cgi-bin/docs/rdoc?v=2020.2;t=hls+guidance;d=200-881.html
WARNING: [HLS 200-881] Unable to enforce a carried constraint (II = 2) between 'dadd' operation ('add', code.cpp:17) and 'dadd' operation ('add', code.cpp:17).
Resolution: For help on HLS 200-881 see www.xilinx.com/cgi-bin/docs/rdoc?v=2020.2;t=hls+guidance;d=200-881.html
WARNING: [HLS 200-881] Unable to enforce a carried constraint (II = 3) between 'dadd' operation ('add', code.cpp:17) and 'dadd' operation ('add', code.cpp:17).
Resolution: For help on HLS 200-881 see www.xilinx.com/cgi-bin/docs/rdoc?v=2020.2;t=hls+guidance;d=200-881.html
WARNING: [HLS 200-881] Unable to enforce a carried constraint (II = 4) between 'dadd' operation ('add', code.cpp:17) and 'dadd' operation ('add', code.cpp:17).
Resolution: For help on HLS 200-881 see www.xilinx.com/cgi-bin/docs/rdoc?v=2020.2;t=hls+guidance;d=200-881.html
WARNING: [HLS 200-881] Unable to enforce a carried constraint (II = 5) between 'dadd' operation ('add', code.cpp:17) and 'dadd' operation ('add', code.cpp:17).
Resolution: For help on HLS 200-881 see www.xilinx.com/cgi-bin/docs/rdoc?v=2020.2;t=hls+guidance;d=200-881.html
WARNING: [HLS 200-881] Unable to enforce a carried constraint (II = 6) between 'dadd' operation ('add', code.cpp:17) and 'dadd' operation ('add', code.cpp:17).
Resolution: For help on HLS 200-881 see www.xilinx.com/cgi-bin/docs/rdoc?v=2020.2;t=hls+guidance;d=200-881.html
INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 7, Depth = 12, loop 'loop_in'
WARNING: [HLS 200-871] Estimated clock period (3.81ns) exceeds the target (target clock period: 3.003ns, clock uncertainty: 0.81081ns, effective delay budget: 2.19219ns).
Resolution: For help on HLS 200-871 see www.xilinx.com/cgi-bin/docs/rdoc?v=2020.2;t=hls+guidance;d=200-871.html
WARNING: [HLS 200-1016] The critical path in module 'reduce_2d_to_1d' consists of the following: 'dadd' operation ('add', code.cpp:17) [40] (1.91 ns)
'phi' operation ('empty_6', code.cpp:17) with incoming values : ('bitcast_ln17', code.cpp:17) ('add', code.cpp:17) [26] (0 ns)
'dadd' operation ('add', code.cpp:17) [40] (1.91 ns)
Resolution: For help on HLS 200-1016 see www.xilinx.com/cgi-bin/docs/rdoc?v=2020.2;t=hls+guidance;d=200-1016.html
INFO: [SCHED 204-11] Finished scheduling.
INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.06 seconds. CPU system time: 0 seconds. Elapsed time: 0.07 seconds; current allocated memory: 179.400 MB.
INFO: [BIND 205-100] Starting micro-architecture generation ...
INFO: [BIND 205-101] Performing variable lifetime analysis.
INFO: [BIND 205-101] Exploring resource sharing.
INFO: [BIND 205-101] Binding ...
INFO: [BIND 205-100] Finished micro-architecture generation.
INFO: [HLS 200-111] Finished Binding: CPU user time: 0.09 seconds. CPU system time: 0 seconds. Elapsed time: 0.08 seconds; current allocated memory: 179.676 MB.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-10] -- Generating RTL for module 'reduce_2d_to_1d'
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [RTGEN 206-500] Setting interface mode on port 'reduce_2d_to_1d/data' to 'ap_memory'.
INFO: [RTGEN 206-500] Setting interface mode on port 'reduce_2d_to_1d/acc' to 'ap_memory'.
INFO: [RTGEN 206-500] Setting interface mode on function 'reduce_2d_to_1d' to 'ap_ctrl_hs'.
INFO: [RTGEN 206-100] Generating core module 'dadd_64ns_64ns_64_8_full_dsp_1': 1 instance(s).
INFO: [RTGEN 206-100] Finished creating RTL model for 'reduce_2d_to_1d'.
INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.06 seconds. CPU system time: 0 seconds. Elapsed time: 0.06 seconds; current allocated memory: 180.199 MB.
INFO: [HLS 200-111] Finished Generating all RTL models: CPU user time: 0.83 seconds. CPU system time: 0.04 seconds. Elapsed time: 1 seconds; current allocated memory: 187.869 MB.
INFO: [VHDL 208-304] Generating VHDL RTL for reduce_2d_to_1d.
INFO: [VLOG 209-307] Generating Verilog RTL for reduce_2d_to_1d.
INFO: [HLS 200-790] **** Loop Constraint Status: All loop constraints were NOT satisfied.
INFO: [HLS 200-789] **** Estimated Fmax: 262.47 MHz
INFO: [HLS 200-111] Finished Command csynth_design CPU user time: 4.68 seconds. CPU system time: 0.41 seconds. Elapsed time: 5.22 seconds; current allocated memory: 187.984 MB.
SOLUTION 1.nointerchange: LLVM_CUSTOM_CMD -slx-prepare-interchange, no Xilinx directives (clock: 333MHz)
INFO: [HLS 200-1510] Running: open_solution -reset 1.nointerchange
INFO: [HLS 200-10] Creating and opening solution '/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/slxplugin_loopinterchange_demo/proj/1.nointerchange'.
INFO: [HLS 200-10] Cleaning up the solution database.
WARNING: [HLS 200-40] No /media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/slxplugin_loopinterchange_demo/proj/1.nointerchange/1.nointerchange.aps file found.
INFO: [HLS 200-1505] Using default flow_target 'vivado'
Resolution: For help on HLS 200-1505 see www.xilinx.com/cgi-bin/docs/rdoc?v=2020.2;t=hls+guidance;d=200-1505.html
INFO: [HLS 200-1510] Running: set_part xcvu9p-flga2104-2-i
INFO: [HLS 200-1510] Running: create_clock -period 333MHz
INFO: [SYN 201-201] Setting up clock 'default' with a period of 3.003ns.
INFO: [HLS 200-1510] Running: ::xilinx_csynth_design
INFO: [HLS 200-111] Finished File checks and directory preparation: CPU user time: 0 seconds. CPU system time: 0.01 seconds. Elapsed time: 0 seconds; current allocated memory: 175.511 MB.
INFO: [HLS 200-10] Analyzing design file 'code.cpp' ...
INFO: [HLS 200-111] Finished Source Code Analysis and Preprocessing: CPU user time: 0.11 seconds. CPU system time: 0.08 seconds. Elapsed time: 0.19 seconds; current allocated memory: 175.519 MB.
INFO: [HLS 200-1022] Execute customized passes: $LLVM_CUSTOM_OPT -load /media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/slxplugin_loopinterchange_demo/slxplugin/lib/slxplugin.so -slx-prepare-for-interchange -slx-remove-directives $LLVM_CUSTOM_INPUT -o $LLVM_CUSTOM_OUTPUT
LLVM_CUSTOM_OPT:/media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis_HLS/2020.2/lnx64/tools/clang-3.9-csynth/bin/opt
LLVM_CUSTOM_INPUT:/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/slxplugin_loopinterchange_demo/proj/1.nointerchange/.autopilot/db/a.g.ld.5.gdce.bc
LLVM_CUSTOM_OUTPUT:/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/slxplugin_loopinterchange_demo/proj/1.nointerchange/.autopilot/db/a.g.ld.6.user.bc
INFO: [HLS 200-777] Using interface defaults for 'Vivado' flow target.
INFO: [HLS 200-111] Finished Compiling Optimization and Transform: CPU user time: 3.37 seconds. CPU system time: 0.3 seconds. Elapsed time: 3.75 seconds; current allocated memory: 175.627 MB.
INFO: [HLS 200-111] Finished Checking Pragmas: CPU user time: 0 seconds. CPU system time: 0 seconds. Elapsed time: 0 seconds; current allocated memory: 175.628 MB.
INFO: [HLS 200-10] Starting code transformations ...
INFO: [HLS 200-111] Finished Standard Transforms: CPU user time: 0.01 seconds. CPU system time: 0 seconds. Elapsed time: 0.01 seconds; current allocated memory: 176.578 MB.
INFO: [HLS 200-10] Checking synthesizability ...
INFO: [HLS 200-111] Finished Checking Synthesizability: CPU user time: 0.01 seconds. CPU system time: 0 seconds. Elapsed time: 0.01 seconds; current allocated memory: 175.775 MB.
INFO: [XFORM 203-510] Pipelining loop 'loop_in' (code.cpp:15) in function 'reduce_2d_to_1d' automatically.
INFO: [HLS 200-111] Finished Loop, function and other optimizations: CPU user time: 0.06 seconds. CPU system time: 0 seconds. Elapsed time: 0.05 seconds; current allocated memory: 196.111 MB.
WARNING: [HLS 200-960] Cannot flatten loop 'loop_out' (code.cpp:14:21) in function 'reduce_2d_to_1d' either the parent loop or sub loop is do-while loop.
Resolution: For help on HLS 200-960 see www.xilinx.com/cgi-bin/docs/rdoc?v=2020.2;t=hls+guidance;d=200-960.html
INFO: [HLS 200-111] Finished Architecture Synthesis: CPU user time: 0.03 seconds. CPU system time: 0 seconds. Elapsed time: 0.03 seconds; current allocated memory: 188.303 MB.
INFO: [HLS 200-10] Starting hardware synthesis ...
INFO: [HLS 200-10] Synthesizing 'reduce_2d_to_1d' ...
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-42] -- Implementing module 'reduce_2d_to_1d'
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [SCHED 204-11] Starting scheduling ...
INFO: [SCHED 204-61] Pipelining loop 'loop_in'.
WARNING: [HLS 200-881] Unable to enforce a carried constraint (II = 1) between 'dadd' operation ('add', code.cpp:17) and 'dadd' operation ('add', code.cpp:17).
Resolution: For help on HLS 200-881 see www.xilinx.com/cgi-bin/docs/rdoc?v=2020.2;t=hls+guidance;d=200-881.html
WARNING: [HLS 200-881] Unable to enforce a carried constraint (II = 2) between 'dadd' operation ('add', code.cpp:17) and 'dadd' operation ('add', code.cpp:17).
Resolution: For help on HLS 200-881 see www.xilinx.com/cgi-bin/docs/rdoc?v=2020.2;t=hls+guidance;d=200-881.html
WARNING: [HLS 200-881] Unable to enforce a carried constraint (II = 3) between 'dadd' operation ('add', code.cpp:17) and 'dadd' operation ('add', code.cpp:17).
Resolution: For help on HLS 200-881 see www.xilinx.com/cgi-bin/docs/rdoc?v=2020.2;t=hls+guidance;d=200-881.html
WARNING: [HLS 200-881] Unable to enforce a carried constraint (II = 4) between 'dadd' operation ('add', code.cpp:17) and 'dadd' operation ('add', code.cpp:17).
Resolution: For help on HLS 200-881 see www.xilinx.com/cgi-bin/docs/rdoc?v=2020.2;t=hls+guidance;d=200-881.html
WARNING: [HLS 200-881] Unable to enforce a carried constraint (II = 5) between 'dadd' operation ('add', code.cpp:17) and 'dadd' operation ('add', code.cpp:17).
Resolution: For help on HLS 200-881 see www.xilinx.com/cgi-bin/docs/rdoc?v=2020.2;t=hls+guidance;d=200-881.html
WARNING: [HLS 200-881] Unable to enforce a carried constraint (II = 6) between 'dadd' operation ('add', code.cpp:17) and 'dadd' operation ('add', code.cpp:17).
Resolution: For help on HLS 200-881 see www.xilinx.com/cgi-bin/docs/rdoc?v=2020.2;t=hls+guidance;d=200-881.html
INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 7, Depth = 11, loop 'loop_in'
WARNING: [HLS 200-871] Estimated clock period (3.81ns) exceeds the target (target clock period: 3.003ns, clock uncertainty: 0.81081ns, effective delay budget: 2.19219ns).
Resolution: For help on HLS 200-871 see www.xilinx.com/cgi-bin/docs/rdoc?v=2020.2;t=hls+guidance;d=200-871.html
WARNING: [HLS 200-1016] The critical path in module 'reduce_2d_to_1d' consists of the following: 'dadd' operation ('add', code.cpp:17) [30] (1.91 ns)
'phi' operation ('empty_6', code.cpp:17) with incoming values : ('bitcast_ln17', code.cpp:17) ('add', code.cpp:17) [21] (0 ns)
'dadd' operation ('add', code.cpp:17) [30] (1.91 ns)
Resolution: For help on HLS 200-1016 see www.xilinx.com/cgi-bin/docs/rdoc?v=2020.2;t=hls+guidance;d=200-1016.html
INFO: [SCHED 204-11] Finished scheduling.
INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.05 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.07 seconds; current allocated memory: 188.445 MB.
INFO: [BIND 205-100] Starting micro-architecture generation ...
INFO: [BIND 205-101] Performing variable lifetime analysis.
INFO: [BIND 205-101] Exploring resource sharing.
INFO: [BIND 205-101] Binding ...
INFO: [BIND 205-100] Finished micro-architecture generation.
INFO: [HLS 200-111] Finished Binding: CPU user time: 0.07 seconds. CPU system time: 0 seconds. Elapsed time: 0.07 seconds; current allocated memory: 188.624 MB.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-10] -- Generating RTL for module 'reduce_2d_to_1d'
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [RTGEN 206-500] Setting interface mode on port 'reduce_2d_to_1d/data' to 'ap_memory'.
INFO: [RTGEN 206-500] Setting interface mode on port 'reduce_2d_to_1d/acc' to 'ap_memory'.
INFO: [RTGEN 206-500] Setting interface mode on function 'reduce_2d_to_1d' to 'ap_ctrl_hs'.
INFO: [RTGEN 206-100] Generating core module 'dadd_64ns_64ns_64_8_full_dsp_1': 1 instance(s).
INFO: [RTGEN 206-100] Finished creating RTL model for 'reduce_2d_to_1d'.
INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.06 seconds. CPU system time: 0 seconds. Elapsed time: 0.05 seconds; current allocated memory: 188.997 MB.
INFO: [HLS 200-111] Finished Generating all RTL models: CPU user time: 0.7 seconds. CPU system time: 0.04 seconds. Elapsed time: 0.74 seconds; current allocated memory: 190.005 MB.
INFO: [VHDL 208-304] Generating VHDL RTL for reduce_2d_to_1d.
INFO: [VLOG 209-307] Generating Verilog RTL for reduce_2d_to_1d.
INFO: [HLS 200-790] **** Loop Constraint Status: All loop constraints were NOT satisfied.
INFO: [HLS 200-789] **** Estimated Fmax: 262.47 MHz
INFO: [HLS 200-111] Finished Command csynth_design CPU user time: 4.54 seconds. CPU system time: 0.44 seconds. Elapsed time: 5.04 seconds; current allocated memory: 190.131 MB.
SOLUTION 2.interchange: LLVM_CUSTOM_CMD -slx-prepare-interchange -slx-loop-interchange, no Xilinx directives (clock: 333MHz)
INFO: [HLS 200-1510] Running: open_solution -reset 2.interchange
INFO: [HLS 200-10] Creating and opening solution '/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/slxplugin_loopinterchange_demo/proj/2.interchange'.
INFO: [HLS 200-10] Cleaning up the solution database.
WARNING: [HLS 200-40] No /media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/slxplugin_loopinterchange_demo/proj/2.interchange/2.interchange.aps file found.
INFO: [HLS 200-1505] Using default flow_target 'vivado'
Resolution: For help on HLS 200-1505 see www.xilinx.com/cgi-bin/docs/rdoc?v=2020.2;t=hls+guidance;d=200-1505.html
INFO: [HLS 200-1510] Running: set_part xcvu9p-flga2104-2-i
INFO: [HLS 200-1510] Running: create_clock -period 333MHz
INFO: [SYN 201-201] Setting up clock 'default' with a period of 3.003ns.
INFO: [HLS 200-1510] Running: ::xilinx_csynth_design
INFO: [HLS 200-111] Finished File checks and directory preparation: CPU user time: 0.01 seconds. CPU system time: 0 seconds. Elapsed time: 0.01 seconds; current allocated memory: 177.487 MB.
INFO: [HLS 200-10] Analyzing design file 'code.cpp' ...
INFO: [HLS 200-111] Finished Source Code Analysis and Preprocessing: CPU user time: 0.12 seconds. CPU system time: 0.08 seconds. Elapsed time: 0.2 seconds; current allocated memory: 177.531 MB.
INFO: [HLS 200-1022] Execute customized passes: $LLVM_CUSTOM_OPT -load /media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/slxplugin_loopinterchange_demo/slxplugin/lib/slxplugin.so -slx-prepare-for-interchange -slx-loop-interchange -slx-remove-directives $LLVM_CUSTOM_INPUT -o $LLVM_CUSTOM_OUTPUT
LLVM_CUSTOM_OPT:/media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis_HLS/2020.2/lnx64/tools/clang-3.9-csynth/bin/opt
LLVM_CUSTOM_INPUT:/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/slxplugin_loopinterchange_demo/proj/2.interchange/.autopilot/db/a.g.ld.5.gdce.bc
LLVM_CUSTOM_OUTPUT:/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/slxplugin_loopinterchange_demo/proj/2.interchange/.autopilot/db/a.g.ld.6.user.bc
SLX-INFO: code.cpp:15:13: _SLXLoopInterchange applied successfully
INFO: [HLS 200-777] Using interface defaults for 'Vivado' flow target.
INFO: [HLS 200-111] Finished Compiling Optimization and Transform: CPU user time: 3.36 seconds. CPU system time: 0.3 seconds. Elapsed time: 3.67 seconds; current allocated memory: 177.608 MB.
INFO: [HLS 200-111] Finished Checking Pragmas: CPU user time: 0 seconds. CPU system time: 0 seconds. Elapsed time: 0 seconds; current allocated memory: 177.609 MB.
INFO: [HLS 200-10] Starting code transformations ...
INFO: [HLS 200-111] Finished Standard Transforms: CPU user time: 0.01 seconds. CPU system time: 0 seconds. Elapsed time: 0.01 seconds; current allocated memory: 178.530 MB.
INFO: [HLS 200-10] Checking synthesizability ...
INFO: [HLS 200-111] Finished Checking Synthesizability: CPU user time: 0.01 seconds. CPU system time: 0 seconds. Elapsed time: 0.02 seconds; current allocated memory: 177.750 MB.
INFO: [XFORM 203-510] Pipelining loop 'loop_out' (code.cpp:14) in function 'reduce_2d_to_1d' automatically.
INFO: [HLS 200-111] Finished Loop, function and other optimizations: CPU user time: 0.06 seconds. CPU system time: 0 seconds. Elapsed time: 0.05 seconds; current allocated memory: 198.051 MB.
WARNING: [HLS 200-960] Cannot flatten loop 'loop_in' (code.cpp:15:13) in function 'reduce_2d_to_1d' either the parent loop or sub loop is do-while loop.
Resolution: For help on HLS 200-960 see www.xilinx.com/cgi-bin/docs/rdoc?v=2020.2;t=hls+guidance;d=200-960.html
INFO: [HLS 200-111] Finished Architecture Synthesis: CPU user time: 0.03 seconds. CPU system time: 0 seconds. Elapsed time: 0.03 seconds; current allocated memory: 190.239 MB.
INFO: [HLS 200-10] Starting hardware synthesis ...
INFO: [HLS 200-10] Synthesizing 'reduce_2d_to_1d' ...
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-42] -- Implementing module 'reduce_2d_to_1d'
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [SCHED 204-11] Starting scheduling ...
INFO: [SCHED 204-61] Pipelining loop 'loop_out'.
INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 12, loop 'loop_out'
INFO: [SCHED 204-11] Finished scheduling.
INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.06 seconds. CPU system time: 0 seconds. Elapsed time: 0.06 seconds; current allocated memory: 190.374 MB.
INFO: [BIND 205-100] Starting micro-architecture generation ...
INFO: [BIND 205-101] Performing variable lifetime analysis.
INFO: [BIND 205-101] Exploring resource sharing.
INFO: [BIND 205-101] Binding ...
INFO: [BIND 205-100] Finished micro-architecture generation.
INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.08 seconds; current allocated memory: 190.552 MB.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-10] -- Generating RTL for module 'reduce_2d_to_1d'
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [RTGEN 206-500] Setting interface mode on port 'reduce_2d_to_1d/data' to 'ap_memory'.
INFO: [RTGEN 206-500] Setting interface mode on port 'reduce_2d_to_1d/acc' to 'ap_memory'.
INFO: [RTGEN 206-500] Setting interface mode on function 'reduce_2d_to_1d' to 'ap_ctrl_hs'.
INFO: [RTGEN 206-100] Generating core module 'dadd_64ns_64ns_64_8_full_dsp_1': 1 instance(s).
INFO: [RTGEN 206-100] Finished creating RTL model for 'reduce_2d_to_1d'.
INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.06 seconds. CPU system time: 0 seconds. Elapsed time: 0.06 seconds; current allocated memory: 190.907 MB.
INFO: [HLS 200-111] Finished Generating all RTL models: CPU user time: 0.77 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.8 seconds; current allocated memory: 191.825 MB.
INFO: [VHDL 208-304] Generating VHDL RTL for reduce_2d_to_1d.
INFO: [VLOG 209-307] Generating Verilog RTL for reduce_2d_to_1d.
INFO: [HLS 200-790] **** Loop Constraint Status: All loop constraints were satisfied.
INFO: [HLS 200-789] **** Estimated Fmax: 524.93 MHz
INFO: [HLS 200-111] Finished Command csynth_design CPU user time: 4.63 seconds. CPU system time: 0.41 seconds. Elapsed time: 5.05 seconds; current allocated memory: 191.955 MB.
SOLUTION 3.vanilla: no LLVM_CUSTOM_CMD, no Xilinx directives (clock: 85MHz)
INFO: [HLS 200-1510] Running: open_solution -reset 3.vanilla
INFO: [HLS 200-10] Creating and opening solution '/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/slxplugin_loopinterchange_demo/proj/3.vanilla'.
INFO: [HLS 200-10] Cleaning up the solution database.
WARNING: [HLS 200-40] No /media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/slxplugin_loopinterchange_demo/proj/3.vanilla/3.vanilla.aps file found.
INFO: [HLS 200-1505] Using default flow_target 'vivado'
Resolution: For help on HLS 200-1505 see www.xilinx.com/cgi-bin/docs/rdoc?v=2020.2;t=hls+guidance;d=200-1505.html
INFO: [HLS 200-1510] Running: set_part xcvu9p-flga2104-2-i
INFO: [HLS 200-1510] Running: create_clock -period 85MHz
INFO: [SYN 201-201] Setting up clock 'default' with a period of 11.765ns.
INFO: [HLS 200-1510] Running: ::xilinx_csynth_design
INFO: [HLS 200-111] Finished File checks and directory preparation: CPU user time: 0 seconds. CPU system time: 0 seconds. Elapsed time: 0 seconds; current allocated memory: 179.284 MB.
INFO: [HLS 200-10] Analyzing design file 'code.cpp' ...
INFO: [HLS 200-111] Finished Source Code Analysis and Preprocessing: CPU user time: 0.11 seconds. CPU system time: 0.1 seconds. Elapsed time: 0.2 seconds; current allocated memory: 179.320 MB.
INFO: [HLS 200-1022] Execute customized passes: $LLVM_CUSTOM_OPT -load /media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/slxplugin_loopinterchange_demo/slxplugin/lib/slxplugin.so -slx-remove-directives $LLVM_CUSTOM_INPUT -o $LLVM_CUSTOM_OUTPUT
LLVM_CUSTOM_OPT:/media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis_HLS/2020.2/lnx64/tools/clang-3.9-csynth/bin/opt
LLVM_CUSTOM_INPUT:/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/slxplugin_loopinterchange_demo/proj/3.vanilla/.autopilot/db/a.g.ld.5.gdce.bc
LLVM_CUSTOM_OUTPUT:/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/slxplugin_loopinterchange_demo/proj/3.vanilla/.autopilot/db/a.g.ld.6.user.bc
INFO: [HLS 200-777] Using interface defaults for 'Vivado' flow target.
INFO: [HLS 200-111] Finished Compiling Optimization and Transform: CPU user time: 3.35 seconds. CPU system time: 0.25 seconds. Elapsed time: 3.63 seconds; current allocated memory: 179.425 MB.
INFO: [HLS 200-111] Finished Checking Pragmas: CPU user time: 0 seconds. CPU system time: 0 seconds. Elapsed time: 0 seconds; current allocated memory: 179.426 MB.
INFO: [HLS 200-10] Starting code transformations ...
INFO: [HLS 200-111] Finished Standard Transforms: CPU user time: 0.01 seconds. CPU system time: 0 seconds. Elapsed time: 0.01 seconds; current allocated memory: 180.382 MB.
INFO: [HLS 200-10] Checking synthesizability ...
INFO: [HLS 200-111] Finished Checking Synthesizability: CPU user time: 0.02 seconds. CPU system time: 0 seconds. Elapsed time: 0.02 seconds; current allocated memory: 179.567 MB.
INFO: [XFORM 203-510] Pipelining loop 'loop_in' (code.cpp:15) in function 'reduce_2d_to_1d' automatically.
INFO: [HLS 200-111] Finished Loop, function and other optimizations: CPU user time: 0.05 seconds. CPU system time: 0 seconds. Elapsed time: 0.05 seconds; current allocated memory: 199.898 MB.
WARNING: [HLS 200-960] Cannot flatten loop 'loop_out' (code.cpp:14:21) in function 'reduce_2d_to_1d' the outer loop is not a perfect loop.
Resolution: For help on HLS 200-960 see www.xilinx.com/cgi-bin/docs/rdoc?v=2020.2;t=hls+guidance;d=200-960.html
INFO: [HLS 200-111] Finished Architecture Synthesis: CPU user time: 0.03 seconds. CPU system time: 0 seconds. Elapsed time: 0.03 seconds; current allocated memory: 192.143 MB.
INFO: [HLS 200-10] Starting hardware synthesis ...
INFO: [HLS 200-10] Synthesizing 'reduce_2d_to_1d' ...
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-42] -- Implementing module 'reduce_2d_to_1d'
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [SCHED 204-11] Starting scheduling ...
INFO: [SCHED 204-61] Pipelining loop 'loop_in'.
INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 5, loop 'loop_in'
WARNING: [HLS 200-871] Estimated clock period (17.012ns) exceeds the target (target clock period: 11.765ns, clock uncertainty: 3.17655ns, effective delay budget: 8.58845ns).
Resolution: For help on HLS 200-871 see www.xilinx.com/cgi-bin/docs/rdoc?v=2020.2;t=hls+guidance;d=200-871.html
WARNING: [HLS 200-1016] The critical path in module 'reduce_2d_to_1d' consists of the following: 'dadd' operation ('add', code.cpp:17) [40] (8.51 ns)
'phi' operation ('empty_6', code.cpp:17) with incoming values : ('bitcast_ln17', code.cpp:17) ('add', code.cpp:17) [26] (0 ns)
'dadd' operation ('add', code.cpp:17) [40] (8.51 ns)
Resolution: For help on HLS 200-1016 see www.xilinx.com/cgi-bin/docs/rdoc?v=2020.2;t=hls+guidance;d=200-1016.html
INFO: [SCHED 204-11] Finished scheduling.
INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.05 seconds. CPU system time: 0 seconds. Elapsed time: 0.06 seconds; current allocated memory: 192.299 MB.
INFO: [BIND 205-100] Starting micro-architecture generation ...
INFO: [BIND 205-101] Performing variable lifetime analysis.
INFO: [BIND 205-101] Exploring resource sharing.
INFO: [BIND 205-101] Binding ...
INFO: [BIND 205-100] Finished micro-architecture generation.
INFO: [HLS 200-111] Finished Binding: CPU user time: 0.05 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.06 seconds; current allocated memory: 192.480 MB.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-10] -- Generating RTL for module 'reduce_2d_to_1d'
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [RTGEN 206-500] Setting interface mode on port 'reduce_2d_to_1d/data' to 'ap_memory'.
INFO: [RTGEN 206-500] Setting interface mode on port 'reduce_2d_to_1d/acc' to 'ap_memory'.
INFO: [RTGEN 206-500] Setting interface mode on function 'reduce_2d_to_1d' to 'ap_ctrl_hs'.
INFO: [RTGEN 206-100] Generating core module 'dadd_64ns_64ns_64_2_full_dsp_1': 1 instance(s).
INFO: [RTGEN 206-100] Finished creating RTL model for 'reduce_2d_to_1d'.
INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.06 seconds. CPU system time: 0 seconds. Elapsed time: 0.05 seconds; current allocated memory: 192.813 MB.
INFO: [HLS 200-111] Finished Generating all RTL models: CPU user time: 0.75 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.79 seconds; current allocated memory: 193.821 MB.
INFO: [VHDL 208-304] Generating VHDL RTL for reduce_2d_to_1d.
INFO: [VLOG 209-307] Generating Verilog RTL for reduce_2d_to_1d.
INFO: [HLS 200-790] **** Loop Constraint Status: All loop constraints were satisfied.
INFO: [HLS 200-789] **** Estimated Fmax: 58.78 MHz
INFO: [HLS 200-111] Finished Command csynth_design CPU user time: 4.53 seconds. CPU system time: 0.39 seconds. Elapsed time: 4.95 seconds; current allocated memory: 193.947 MB.
SOLUTION 4.nointerchange: LLVM_CUSTOM_CMD -slx-prepare-interchange, no Xilinx directives (clock: 85MHz)
INFO: [HLS 200-1510] Running: open_solution -reset 4.nointerchange
INFO: [HLS 200-10] Creating and opening solution '/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/slxplugin_loopinterchange_demo/proj/4.nointerchange'.
INFO: [HLS 200-10] Cleaning up the solution database.
WARNING: [HLS 200-40] No /media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/slxplugin_loopinterchange_demo/proj/4.nointerchange/4.nointerchange.aps file found.
INFO: [HLS 200-1505] Using default flow_target 'vivado'
Resolution: For help on HLS 200-1505 see www.xilinx.com/cgi-bin/docs/rdoc?v=2020.2;t=hls+guidance;d=200-1505.html
INFO: [HLS 200-1510] Running: set_part xcvu9p-flga2104-2-i
INFO: [HLS 200-1510] Running: create_clock -period 85MHz
INFO: [SYN 201-201] Setting up clock 'default' with a period of 11.765ns.
INFO: [HLS 200-1510] Running: ::xilinx_csynth_design
INFO: [HLS 200-111] Finished File checks and directory preparation: CPU user time: 0 seconds. CPU system time: 0.01 seconds. Elapsed time: 0 seconds; current allocated memory: 181.182 MB.
INFO: [HLS 200-10] Analyzing design file 'code.cpp' ...
INFO: [HLS 200-111] Finished Source Code Analysis and Preprocessing: CPU user time: 0.11 seconds. CPU system time: 0.09 seconds. Elapsed time: 0.2 seconds; current allocated memory: 181.220 MB.
INFO: [HLS 200-1022] Execute customized passes: $LLVM_CUSTOM_OPT -load /media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/slxplugin_loopinterchange_demo/slxplugin/lib/slxplugin.so -slx-prepare-for-interchange -slx-remove-directives $LLVM_CUSTOM_INPUT -o $LLVM_CUSTOM_OUTPUT
LLVM_CUSTOM_OPT:/media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis_HLS/2020.2/lnx64/tools/clang-3.9-csynth/bin/opt
LLVM_CUSTOM_INPUT:/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/slxplugin_loopinterchange_demo/proj/4.nointerchange/.autopilot/db/a.g.ld.5.gdce.bc
LLVM_CUSTOM_OUTPUT:/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/slxplugin_loopinterchange_demo/proj/4.nointerchange/.autopilot/db/a.g.ld.6.user.bc
INFO: [HLS 200-777] Using interface defaults for 'Vivado' flow target.
INFO: [HLS 200-111] Finished Compiling Optimization and Transform: CPU user time: 3.38 seconds. CPU system time: 0.22 seconds. Elapsed time: 3.6 seconds; current allocated memory: 181.295 MB.
INFO: [HLS 200-111] Finished Checking Pragmas: CPU user time: 0 seconds. CPU system time: 0 seconds. Elapsed time: 0.01 seconds; current allocated memory: 181.295 MB.
INFO: [HLS 200-10] Starting code transformations ...
INFO: [HLS 200-111] Finished Standard Transforms: CPU user time: 0.01 seconds. CPU system time: 0 seconds. Elapsed time: 0 seconds; current allocated memory: 182.255 MB.
INFO: [HLS 200-10] Checking synthesizability ...
INFO: [HLS 200-111] Finished Checking Synthesizability: CPU user time: 0.01 seconds. CPU system time: 0 seconds. Elapsed time: 0.02 seconds; current allocated memory: 181.438 MB.
INFO: [XFORM 203-510] Pipelining loop 'loop_in' (code.cpp:15) in function 'reduce_2d_to_1d' automatically.
INFO: [HLS 200-111] Finished Loop, function and other optimizations: CPU user time: 0.05 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.05 seconds; current allocated memory: 201.744 MB.
WARNING: [HLS 200-960] Cannot flatten loop 'loop_out' (code.cpp:14:21) in function 'reduce_2d_to_1d' either the parent loop or sub loop is do-while loop.
Resolution: For help on HLS 200-960 see www.xilinx.com/cgi-bin/docs/rdoc?v=2020.2;t=hls+guidance;d=200-960.html
INFO: [HLS 200-111] Finished Architecture Synthesis: CPU user time: 0.03 seconds. CPU system time: 0 seconds. Elapsed time: 0.03 seconds; current allocated memory: 193.936 MB.
INFO: [HLS 200-10] Starting hardware synthesis ...
INFO: [HLS 200-10] Synthesizing 'reduce_2d_to_1d' ...
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-42] -- Implementing module 'reduce_2d_to_1d'
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [SCHED 204-11] Starting scheduling ...
INFO: [SCHED 204-61] Pipelining loop 'loop_in'.
INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 4, loop 'loop_in'
WARNING: [HLS 200-871] Estimated clock period (17.012ns) exceeds the target (target clock period: 11.765ns, clock uncertainty: 3.17655ns, effective delay budget: 8.58845ns).
Resolution: For help on HLS 200-871 see www.xilinx.com/cgi-bin/docs/rdoc?v=2020.2;t=hls+guidance;d=200-871.html
WARNING: [HLS 200-1016] The critical path in module 'reduce_2d_to_1d' consists of the following: 'dadd' operation ('add', code.cpp:17) [30] (8.51 ns)
'phi' operation ('empty_6', code.cpp:17) with incoming values : ('bitcast_ln17', code.cpp:17) ('add', code.cpp:17) [21] (0 ns)
'dadd' operation ('add', code.cpp:17) [30] (8.51 ns)
Resolution: For help on HLS 200-1016 see www.xilinx.com/cgi-bin/docs/rdoc?v=2020.2;t=hls+guidance;d=200-1016.html
INFO: [SCHED 204-11] Finished scheduling.
INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.05 seconds. CPU system time: 0 seconds. Elapsed time: 0.04 seconds; current allocated memory: 194.055 MB.
INFO: [BIND 205-100] Starting micro-architecture generation ...
INFO: [BIND 205-101] Performing variable lifetime analysis.
INFO: [BIND 205-101] Exploring resource sharing.
INFO: [BIND 205-101] Binding ...
INFO: [BIND 205-100] Finished micro-architecture generation.
INFO: [HLS 200-111] Finished Binding: CPU user time: 0.05 seconds. CPU system time: 0 seconds. Elapsed time: 0.05 seconds; current allocated memory: 194.211 MB.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-10] -- Generating RTL for module 'reduce_2d_to_1d'
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [RTGEN 206-500] Setting interface mode on port 'reduce_2d_to_1d/data' to 'ap_memory'.
INFO: [RTGEN 206-500] Setting interface mode on port 'reduce_2d_to_1d/acc' to 'ap_memory'.
INFO: [RTGEN 206-500] Setting interface mode on function 'reduce_2d_to_1d' to 'ap_ctrl_hs'.
INFO: [RTGEN 206-100] Generating core module 'dadd_64ns_64ns_64_2_full_dsp_1': 1 instance(s).
INFO: [RTGEN 206-100] Finished creating RTL model for 'reduce_2d_to_1d'.
INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.04 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.04 seconds; current allocated memory: 194.491 MB.
INFO: [HLS 200-111] Finished Generating all RTL models: CPU user time: 0.77 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.8 seconds; current allocated memory: 195.452 MB.
INFO: [VHDL 208-304] Generating VHDL RTL for reduce_2d_to_1d.
INFO: [VLOG 209-307] Generating Verilog RTL for reduce_2d_to_1d.
INFO: [HLS 200-790] **** Loop Constraint Status: All loop constraints were satisfied.
INFO: [HLS 200-789] **** Estimated Fmax: 58.78 MHz
INFO: [HLS 200-111] Finished Command csynth_design CPU user time: 4.56 seconds. CPU system time: 0.36 seconds. Elapsed time: 4.91 seconds; current allocated memory: 195.548 MB.
SOLUTION 5.interchange: LLVM_CUSTOM_CMD -slx-prepare-interchange -slx-loop-interchange, no Xilinx directives (clock: 85MHz)
INFO: [HLS 200-1510] Running: open_solution -reset 5.interchange
INFO: [HLS 200-10] Creating and opening solution '/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/slxplugin_loopinterchange_demo/proj/5.interchange'.
INFO: [HLS 200-10] Cleaning up the solution database.
WARNING: [HLS 200-40] No /media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/slxplugin_loopinterchange_demo/proj/5.interchange/5.interchange.aps file found.
INFO: [HLS 200-1505] Using default flow_target 'vivado'
Resolution: For help on HLS 200-1505 see www.xilinx.com/cgi-bin/docs/rdoc?v=2020.2;t=hls+guidance;d=200-1505.html
INFO: [HLS 200-1510] Running: set_part xcvu9p-flga2104-2-i
INFO: [HLS 200-1510] Running: create_clock -period 85MHz
INFO: [SYN 201-201] Setting up clock 'default' with a period of 11.765ns.
INFO: [HLS 200-1510] Running: ::xilinx_csynth_design
INFO: [HLS 200-111] Finished File checks and directory preparation: CPU user time: 0.01 seconds. CPU system time: 0 seconds. Elapsed time: 0 seconds; current allocated memory: 182.924 MB.
INFO: [HLS 200-10] Analyzing design file 'code.cpp' ...
INFO: [HLS 200-111] Finished Source Code Analysis and Preprocessing: CPU user time: 0.1 seconds. CPU system time: 0.08 seconds. Elapsed time: 0.21 seconds; current allocated memory: 182.933 MB.
INFO: [HLS 200-1022] Execute customized passes: $LLVM_CUSTOM_OPT -load /media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/slxplugin_loopinterchange_demo/slxplugin/lib/slxplugin.so -slx-prepare-for-interchange -slx-loop-interchange -slx-remove-directives $LLVM_CUSTOM_INPUT -o $LLVM_CUSTOM_OUTPUT
LLVM_CUSTOM_OPT:/media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis_HLS/2020.2/lnx64/tools/clang-3.9-csynth/bin/opt
LLVM_CUSTOM_INPUT:/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/slxplugin_loopinterchange_demo/proj/5.interchange/.autopilot/db/a.g.ld.5.gdce.bc
LLVM_CUSTOM_OUTPUT:/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/slxplugin_loopinterchange_demo/proj/5.interchange/.autopilot/db/a.g.ld.6.user.bc
SLX-INFO: code.cpp:15:13: _SLXLoopInterchange applied successfully
INFO: [HLS 200-777] Using interface defaults for 'Vivado' flow target.
INFO: [HLS 200-111] Finished Compiling Optimization and Transform: CPU user time: 3.41 seconds. CPU system time: 0.24 seconds. Elapsed time: 3.66 seconds; current allocated memory: 183.038 MB.
INFO: [HLS 200-111] Finished Checking Pragmas: CPU user time: 0 seconds. CPU system time: 0 seconds. Elapsed time: 0 seconds; current allocated memory: 183.039 MB.
INFO: [HLS 200-10] Starting code transformations ...
INFO: [HLS 200-111] Finished Standard Transforms: CPU user time: 0.01 seconds. CPU system time: 0 seconds. Elapsed time: 0.01 seconds; current allocated memory: 183.960 MB.
INFO: [HLS 200-10] Checking synthesizability ...
INFO: [HLS 200-111] Finished Checking Synthesizability: CPU user time: 0.01 seconds. CPU system time: 0 seconds. Elapsed time: 0.01 seconds; current allocated memory: 183.192 MB.
INFO: [XFORM 203-510] Pipelining loop 'loop_out' (code.cpp:14) in function 'reduce_2d_to_1d' automatically.
INFO: [HLS 200-111] Finished Loop, function and other optimizations: CPU user time: 0.05 seconds. CPU system time: 0 seconds. Elapsed time: 0.06 seconds; current allocated memory: 203.493 MB.
WARNING: [HLS 200-960] Cannot flatten loop 'loop_in' (code.cpp:15:13) in function 'reduce_2d_to_1d' either the parent loop or sub loop is do-while loop.
Resolution: For help on HLS 200-960 see www.xilinx.com/cgi-bin/docs/rdoc?v=2020.2;t=hls+guidance;d=200-960.html
INFO: [HLS 200-111] Finished Architecture Synthesis: CPU user time: 0.03 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.03 seconds; current allocated memory: 195.673 MB.
INFO: [HLS 200-10] Starting hardware synthesis ...
INFO: [HLS 200-10] Synthesizing 'reduce_2d_to_1d' ...
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-42] -- Implementing module 'reduce_2d_to_1d'
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [SCHED 204-11] Starting scheduling ...
INFO: [SCHED 204-61] Pipelining loop 'loop_out'.
INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 5, loop 'loop_out'
INFO: [SCHED 204-11] Finished scheduling.
INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.03 seconds. CPU system time: 0 seconds. Elapsed time: 0.05 seconds; current allocated memory: 195.790 MB.
INFO: [BIND 205-100] Starting micro-architecture generation ...
INFO: [BIND 205-101] Performing variable lifetime analysis.
INFO: [BIND 205-101] Exploring resource sharing.
INFO: [BIND 205-101] Binding ...
INFO: [BIND 205-100] Finished micro-architecture generation.
INFO: [HLS 200-111] Finished Binding: CPU user time: 0.06 seconds. CPU system time: 0 seconds. Elapsed time: 0.05 seconds; current allocated memory: 195.950 MB.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-10] -- Generating RTL for module 'reduce_2d_to_1d'
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [RTGEN 206-500] Setting interface mode on port 'reduce_2d_to_1d/data' to 'ap_memory'.
INFO: [RTGEN 206-500] Setting interface mode on port 'reduce_2d_to_1d/acc' to 'ap_memory'.
INFO: [RTGEN 206-500] Setting interface mode on function 'reduce_2d_to_1d' to 'ap_ctrl_hs'.
INFO: [RTGEN 206-100] Generating core module 'dadd_64ns_64ns_64_2_full_dsp_1': 1 instance(s).
INFO: [RTGEN 206-100] Finished creating RTL model for 'reduce_2d_to_1d'.
INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.04 seconds. CPU system time: 0 seconds. Elapsed time: 0.04 seconds; current allocated memory: 196.229 MB.
INFO: [HLS 200-111] Finished Generating all RTL models: CPU user time: 0.75 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.75 seconds; current allocated memory: 197.128 MB.
INFO: [VHDL 208-304] Generating VHDL RTL for reduce_2d_to_1d.
INFO: [VLOG 209-307] Generating Verilog RTL for reduce_2d_to_1d.
INFO: [HLS 200-790] **** Loop Constraint Status: All loop constraints were satisfied.
INFO: [HLS 200-789] **** Estimated Fmax: 117.56 MHz
INFO: [HLS 200-111] Finished Command csynth_design CPU user time: 4.56 seconds. CPU system time: 0.35 seconds. Elapsed time: 4.94 seconds; current allocated memory: 197.256 MB.
INFO: [HLS 200-112] Total CPU user time: 31.55 seconds. Total CPU system time: 3.04 seconds. Total elapsed time: 34.01 seconds; peak allocated memory: 203.493 MB.
INFO: [Common 17-206] Exiting vitis_hls at Mon Mar 15 19:52:12 2021...
指示子を追加した。%HLS ARRAY_PARTITION variable=line_buf dim=1 factor=2 block
masaaki@masaaki-H110M4-M01:/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/lap_filter_axis_RGB10_autoAP$ vitis_hls run_hls.tcl
****** Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit)
**** SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
**** IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020
** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
source /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis_HLS/2020.2/scripts/vitis_hls/hls.tcl -notrace
INFO: [HLS 200-10] Running '/media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis_HLS/2020.2/bin/unwrapped/lnx64.o/vitis_hls'
INFO: [HLS 200-10] For user 'masaaki' on host 'masaaki-H110M4-M01' (Linux_x86_64 version 4.15.0-136-generic) on Sun Mar 14 21:25:20 JST 2021
INFO: [HLS 200-10] On os Ubuntu 18.04.5 LTS
INFO: [HLS 200-10] In directory '/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/lap_filter_axis_RGB10_autoAP'
WARNING: [HLS 200-40] Environment variable 'C_INCLUDE_PATH' is set to :/usr/local/cuda/include.
Sourcing Tcl script 'run_hls.tcl'
INFO: [HLS 200-1510] Running: open_project -reset proj
INFO: [HLS 200-10] Creating and opening project '/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/lap_filter_axis_RGB10_autoAP/proj'.
INFO: [HLS 200-1510] Running: add_files lap_filter_axis_RBG10.cpp
INFO: [HLS 200-10] Adding design file 'lap_filter_axis_RBG10.cpp' to the project
INFO: [HLS 200-1510] Running: set_top lap_filter_axis
INFO: [HLS 200-1510] Running: open_solution -reset solution1
INFO: [HLS 200-10] Creating and opening solution '/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/lap_filter_axis_RGB10_autoAP/proj/solution1'.
INFO: [HLS 200-10] Cleaning up the solution database.
WARNING: [HLS 200-40] No /media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/lap_filter_axis_RGB10_autoAP/proj/solution1/solution1.aps file found.
INFO: [HLS 200-1505] Using default flow_target 'vivado'
Resolution: For help on HLS 200-1505 see www.xilinx.com/cgi-bin/docs/rdoc?v=2020.2;t=hls+guidance;d=200-1505.html
INFO: [HLS 200-1510] Running: set_part xczu3eg-sbva484-1-e
INFO: [HLS 200-10] Setting target device to 'xczu3eg-sbva484-1-e'
INFO: [HLS 200-1510] Running: create_clock -period 10
INFO: [SYN 201-201] Setting up clock 'default' with a period of 10ns.
INFO: [HLS 200-1510] Running: csynth_design
INFO: [HLS 200-111] Finished File checks and directory preparation: CPU user time: 0 seconds. CPU system time: 0 seconds. Elapsed time: 0 seconds; current allocated memory: 162.794 MB.
INFO: [HLS 200-10] Analyzing design file 'lap_filter_axis_RBG10.cpp' ...
WARNING: [HLS 207-5510] 'Resource pragma' is deprecated, and it will be removed in future release. It is suggested to replace it with 'bind_op/bind_storage pragma'.: lap_filter_axis_RBG10.cpp:27:9
INFO: [HLS 200-111] Finished Source Code Analysis and Preprocessing: CPU user time: 3.62 seconds. CPU system time: 0.29 seconds. Elapsed time: 3.19 seconds; current allocated memory: 164.399 MB.
INFO: [HLS 200-1022] Execute customized passes: $LLVM_CUSTOM_OPT -always-inline -mem2reg -gvn -reflow-simplify-type -instcombine -mem2reg -gvn -indvars -load $::env(HLS_LLVM_PLUGIN_DIR)/LLVMMemoryPartition.so -auto-memory-partition $LLVM_CUSTOM_INPUT -o $LLVM_CUSTOM_OUTPUT
LLVM_CUSTOM_OPT:/media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis_HLS/2020.2/lnx64/tools/clang-3.9-csynth/bin/opt
LLVM_CUSTOM_INPUT:/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/lap_filter_axis_RGB10_autoAP/proj/solution1/.autopilot/db/a.g.ld.5.gdce.bc
LLVM_CUSTOM_OUTPUT:/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/lap_filter_axis_RGB10_autoAP/proj/solution1/.autopilot/db/a.g.ld.6.user.bc
INFO: [AUTO 101] Generating 1 array partition pragma(s) automatically
INFO: [HLS 200-777] Using interface defaults for 'Vivado' flow target.
INFO: [HLS 214-186] Unrolling loop 'Loop5' (lap_filter_axis_RBG10.cpp:46:13) in function 'lap_filter_axis' completely with a factor of 2 (lap_filter_axis_RBG10.cpp:46:13)
INFO: [HLS 214-178] Inlining function 'conv_rbg2y10(int)' into 'lap_filter_axis(hls::stream<hls::axis<ap_int<32>, 1ul, 1ul, 1ul>, 0>&, hls::stream<hls::axis<ap_int<32>, 1ul, 1ul, 1ul>, 0>&, int)' (lap_filter_axis_RBG10.cpp:16:0)
INFO: [HLS 214-178] Inlining function 'laplacian_fil(int, int, int, int, int, int, int, int, int)' into 'lap_filter_axis(hls::stream<hls::axis<ap_int<32>, 1ul, 1ul, 1ul>, 0>&, hls::stream<hls::axis<ap_int<32>, 1ul, 1ul, 1ul>, 0>&, int)' (lap_filter_axis_RBG10.cpp:16:0)
INFO: [HLS 200-111] Finished Compiling Optimization and Transform: CPU user time: 3.85 seconds. CPU system time: 0.23 seconds. Elapsed time: 4.18 seconds; current allocated memory: 166.336 MB.
INFO: [HLS 200-111] Finished Checking Pragmas: CPU user time: 0 seconds. CPU system time: 0 seconds. Elapsed time: 0 seconds; current allocated memory: 166.339 MB.
INFO: [HLS 200-10] Starting code transformations ...
INFO: [HLS 200-111] Finished Standard Transforms: CPU user time: 0.07 seconds. CPU system time: 0 seconds. Elapsed time: 0.11 seconds; current allocated memory: 173.464 MB.
INFO: [HLS 200-10] Checking synthesizability ...
INFO: [HLS 200-111] Finished Checking Synthesizability: CPU user time: 0.11 seconds. CPU system time: 0 seconds. Elapsed time: 0.1 seconds; current allocated memory: 181.785 MB.
INFO: [XFORM 203-510] Pipelining loop 'Loop1' in function 'lap_filter_axis' automatically.
INFO: [XFORM 203-502] Unrolling all sub-loops inside loop 'Loop3' (lap_filter_axis_RBG10.cpp:22) in function 'lap_filter_axis' for pipelining.
INFO: [HLS 200-489] Unrolling loop 'Loop4' (lap_filter_axis_RBG10.cpp:46) in function 'lap_filter_axis' completely with a factor of 3.
INFO: [XFORM 203-101] Partitioning array 'pix_mat' (lap_filter_axis_RBG10.cpp:29) in dimension 1 completely.
INFO: [XFORM 203-101] Partitioning array 'line_buf' (lap_filter_axis_RBG10.cpp:25) in dimension 1 completely.
INFO: [XFORM 203-102] Automatically partitioning small array 'pix_mat.0' (lap_filter_axis_RBG10.cpp:29) completely based on array size.
INFO: [XFORM 203-102] Automatically partitioning small array 'pix_mat.1' (lap_filter_axis_RBG10.cpp:29) completely based on array size.
INFO: [XFORM 203-102] Automatically partitioning small array 'pix_mat.2' (lap_filter_axis_RBG10.cpp:29) completely based on array size.
INFO: [XFORM 203-101] Partitioning array 'pix_mat.0' (lap_filter_axis_RBG10.cpp:29) in dimension 1 completely.
INFO: [XFORM 203-101] Partitioning array 'pix_mat.1' (lap_filter_axis_RBG10.cpp:29) in dimension 1 completely.
INFO: [XFORM 203-101] Partitioning array 'pix_mat.2' (lap_filter_axis_RBG10.cpp:29) in dimension 1 completely.
INFO: [XFORM 203-11] Balancing expressions in function 'lap_filter_axis' (lap_filter_axis_RBG10.cpp:16)...5 expression(s) balanced.
INFO: [HLS 200-111] Finished Loop, function and other optimizations: CPU user time: 0.28 seconds. CPU system time: 0 seconds. Elapsed time: 0.32 seconds; current allocated memory: 212.423 MB.
INFO: [XFORM 203-541] Flattening a loop nest 'Loop2' (lap_filter_axis_RBG10.cpp:40:20) in function 'lap_filter_axis'.
INFO: [HLS 200-472] Inferring partial write operation for 'line_buf[0]' (lap_filter_axis_RBG10.cpp:57:19)
INFO: [HLS 200-472] Inferring partial write operation for 'line_buf[1]' (lap_filter_axis_RBG10.cpp:58:19)
INFO: [HLS 200-111] Finished Architecture Synthesis: CPU user time: 0.17 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.2 seconds; current allocated memory: 209.959 MB.
INFO: [HLS 200-10] Starting hardware synthesis ...
INFO: [HLS 200-10] Synthesizing 'lap_filter_axis' ...
WARNING: [SYN 201-107] Renaming port name 'lap_filter_axis/function' to 'lap_filter_axis/function_r' to avoid the conflict with HDL keywords or other object names.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-42] -- Implementing module 'lap_filter_axis'
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [SCHED 204-11] Starting scheduling ...
INFO: [HLS 200-486] Changing DSP48 latency (root=mul_ln101) to 3 in order to utilize available DSP registers.
INFO: [HLS 200-486] Changing DSP48 latency (root=mul_ln101_2) to 3 in order to utilize available DSP registers.
INFO: [HLS 200-486] Changing DSP48 latency (root=mul_ln101_1) to 3 in order to utilize available DSP registers.
INFO: [SCHED 204-61] Pipelining loop 'Loop1'.
INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 1, loop 'Loop1'
INFO: [SCHED 204-61] Pipelining loop 'Loop2_Loop3'.
INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 9, loop 'Loop2_Loop3'
INFO: [SCHED 204-11] Finished scheduling.
INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.1 seconds. CPU system time: 0 seconds. Elapsed time: 0.11 seconds; current allocated memory: 210.623 MB.
INFO: [BIND 205-100] Starting micro-architecture generation ...
INFO: [BIND 205-101] Performing variable lifetime analysis.
INFO: [BIND 205-101] Exploring resource sharing.
WARNING: [BIND 205-102] The specified resource core for memory 'line_buf_0' will be ignored if a simpler one can be used.
WARNING: [BIND 205-102] The specified resource core for memory 'line_buf_1' will be ignored if a simpler one can be used.
INFO: [BIND 205-101] Binding ...
INFO: [BIND 205-100] Finished micro-architecture generation.
INFO: [HLS 200-111] Finished Binding: CPU user time: 0.11 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.12 seconds; current allocated memory: 211.361 MB.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-10] -- Generating RTL for module 'lap_filter_axis'
INFO: [HLS 200-10] ----------------------------------------------------------------
WARNING: [RTGEN 206-101] Design contains AXI ports. Reset is fixed to synchronous and active low.
INFO: [RTGEN 206-500] Setting interface mode on port 'lap_filter_axis/ins_V_data_V' to 'axis' (register, both mode).
INFO: [RTGEN 206-500] Setting interface mode on port 'lap_filter_axis/ins_V_keep_V' to 'axis' (register, both mode).
INFO: [RTGEN 206-500] Setting interface mode on port 'lap_filter_axis/ins_V_strb_V' to 'axis' (register, both mode).
INFO: [RTGEN 206-500] Setting interface mode on port 'lap_filter_axis/ins_V_user_V' to 'axis' (register, both mode).
INFO: [RTGEN 206-500] Setting interface mode on port 'lap_filter_axis/ins_V_last_V' to 'axis' (register, both mode).
INFO: [RTGEN 206-500] Setting interface mode on port 'lap_filter_axis/ins_V_id_V' to 'axis' (register, both mode).
INFO: [RTGEN 206-500] Setting interface mode on port 'lap_filter_axis/ins_V_dest_V' to 'axis' (register, both mode).
INFO: [RTGEN 206-500] Setting interface mode on port 'lap_filter_axis/outs_V_data_V' to 'axis' (register, both mode).
INFO: [RTGEN 206-500] Setting interface mode on port 'lap_filter_axis/outs_V_keep_V' to 'axis' (register, both mode).
INFO: [RTGEN 206-500] Setting interface mode on port 'lap_filter_axis/outs_V_strb_V' to 'axis' (register, both mode).
INFO: [RTGEN 206-500] Setting interface mode on port 'lap_filter_axis/outs_V_user_V' to 'axis' (register, both mode).
INFO: [RTGEN 206-500] Setting interface mode on port 'lap_filter_axis/outs_V_last_V' to 'axis' (register, both mode).
INFO: [RTGEN 206-500] Setting interface mode on port 'lap_filter_axis/outs_V_id_V' to 'axis' (register, both mode).
INFO: [RTGEN 206-500] Setting interface mode on port 'lap_filter_axis/outs_V_dest_V' to 'axis' (register, both mode).
INFO: [RTGEN 206-500] Setting interface mode on port 'lap_filter_axis/function_r' to 's_axilite & ap_none'.
INFO: [RTGEN 206-500] Setting interface mode on function 'lap_filter_axis' to 's_axilite & ap_ctrl_hs'.
INFO: [RTGEN 206-100] Bundling port 'return' and 'function_r' to AXI-Lite port control.
INFO: [RTGEN 206-100] Generating core module 'mac_muladd_10ns_6ns_18ns_18_4_1': 1 instance(s).
INFO: [RTGEN 206-100] Generating core module 'mac_muladd_10ns_8ns_18ns_18_4_1': 1 instance(s).
INFO: [RTGEN 206-100] Generating core module 'mul_20s_22ns_32_1_1': 1 instance(s).
INFO: [RTGEN 206-100] Generating core module 'mul_mul_10ns_9ns_18_4_1': 1 instance(s).
INFO: [RTGEN 206-100] Finished creating RTL model for 'lap_filter_axis'.
INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.18 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.22 seconds; current allocated memory: 212.832 MB.
INFO: [RTMG 210-282] Generating pipelined core: 'lap_filter_axis_mul_20s_22ns_32_1_1_Multiplier_0'
INFO: [RTMG 210-278] Implementing memory 'lap_filter_axis_line_buf_0_ram (RAM_2P)' using auto RAMs.
INFO: [RTMG 210-278] Implementing memory 'lap_filter_axis_line_buf_1_ram (RAM_2P)' using auto RAMs.
INFO: [HLS 200-111] Finished Generating all RTL models: CPU user time: 1.37 seconds. CPU system time: 0.07 seconds. Elapsed time: 1.44 seconds; current allocated memory: 222.812 MB.
INFO: [VHDL 208-304] Generating VHDL RTL for lap_filter_axis.
INFO: [VLOG 209-307] Generating Verilog RTL for lap_filter_axis.
INFO: [HLS 200-790] **** Loop Constraint Status: All loop constraints were satisfied.
INFO: [HLS 200-789] **** Estimated Fmax: 143.74 MHz
INFO: [HLS 200-111] Finished Command csynth_design CPU user time: 9.97 seconds. CPU system time: 0.62 seconds. Elapsed time: 10.08 seconds; current allocated memory: 223.207 MB.
INFO: [HLS 200-112] Total CPU user time: 12 seconds. Total CPU system time: 0.99 seconds. Total elapsed time: 11.59 seconds; peak allocated memory: 222.812 MB.
INFO: [Common 17-206] Exiting vitis_hls at Sun Mar 14 21:25:31 2021...
m
%HLS ARRAY_PARTITION variable=a_buf cyclic factor=8 dim=1
%HLS ARRAY_PARTITION variable=b_buf cyclic factor=8 dim=1
%HLS ARRAY_PARTITION variable=c_buf cyclic factor=8 dim=1
VitisHLS内でauto_array_partitionプラグインを使用する方法。plugins / auto_array_partitionプラグインをビルドする必要があります。ローカルのLLVMビルドは必要ありません。
if { ![info exists ::env(HLS_LLVM_PLUGIN_DIR)] } {
# Use plugin example directory as default build directory
set ::env(HLS_LLVM_PLUGIN_DIR) [file normalize ../../plugins/auto_array_partition]
}
if { ![file exists $::env(HLS_LLVM_PLUGIN_DIR)/LLVMMemoryPartition.so] } {
error "Must build LLVMMemoryPartition.so before running this example"
}
### The following variable must be set before csynth_design
# Do not use global namespace (::) for variables used in LVM_CUSTOM_CMD
set ::LLVM_CUSTOM_CMD {$LLVM_CUSTOM_OPT -always-inline -mem2reg -gvn -reflow-simplify-type -instcombine -mem2reg -gvn -indvars -load $::env(HLS_LLVM_PLUGIN_DIR)/LLVMMemoryPartition.so -auto-memory-partition $LLVM_CUSTOM_INPUT -o $LLVM_CUSTOM_OUTPUT}
masaaki@masaaki-H110M4-M01:/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/plugin_analyze_rename_flow_demo$ vitis_hls run_hls.tcl
****** Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit)
**** SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
**** IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020
** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
source /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis_HLS/2020.2/scripts/vitis_hls/hls.tcl -notrace
INFO: [HLS 200-10] Running '/media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis_HLS/2020.2/bin/unwrapped/lnx64.o/vitis_hls'
INFO: [HLS 200-10] For user 'masaaki' on host 'masaaki-H110M4-M01' (Linux_x86_64 version 4.15.0-136-generic) on Fri Mar 12 03:53:25 JST 2021
INFO: [HLS 200-10] On os Ubuntu 18.04.5 LTS
INFO: [HLS 200-10] In directory '/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/plugin_analyze_rename_flow_demo'
WARNING: [HLS 200-40] Environment variable 'C_INCLUDE_PATH' is set to :/usr/local/cuda/include.
Sourcing Tcl script 'run_hls.tcl'
INFO: [HLS 200-1510] Running: open_project -reset proj
INFO: [HLS 200-10] Creating and opening project '/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/plugin_analyze_rename_flow_demo/proj'.
INFO: [HLS 200-1510] Running: add_files hls_example.cpp
INFO: [HLS 200-10] Adding design file 'hls_example.cpp' to the project
INFO: [HLS 200-1510] Running: add_files -tb hls_example.cpp
INFO: [HLS 200-10] Adding test bench file 'hls_example.cpp' to the project
INFO: [HLS 200-1510] Running: set_top example
INFO: [HLS 200-1510] Running: open_solution -reset solution1
INFO: [HLS 200-10] Creating and opening solution '/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/plugin_analyze_rename_flow_demo/proj/solution1'.
INFO: [HLS 200-10] Cleaning up the solution database.
WARNING: [HLS 200-40] No /media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/plugin_analyze_rename_flow_demo/proj/solution1/solution1.aps file found.
INFO: [HLS 200-1505] Using default flow_target 'vivado'
Resolution: For help on HLS 200-1505 see www.xilinx.com/cgi-bin/docs/rdoc?v=2020.2;t=hls+guidance;d=200-1505.html
INFO: [HLS 200-1510] Running: set_part artix7
INFO: [HLS 200-10] Setting target device to 'xc7a12ti-csg325-1L'
INFO: [HLS 200-1510] Running: create_clock -period 300MHz
INFO: [SYN 201-201] Setting up clock 'default' with a period of 3.333ns.
INFO: [HLS 200-1510] Running: csim_design
INFO: [SIM 211-2] *************** CSIM start ***************
INFO: [SIM 211-4] CSIM will launch GCC as the compiler.
Compiling ../../../../hls_example.cpp in debug mode
Generating csim.exe
Test passed.
INFO: [SIM 211-1] CSim done with 0 errors.
INFO: [SIM 211-3] *************** CSIM finish ***************
INFO: [HLS 200-111] Finished Command csim_design CPU user time: 0.84 seconds. CPU system time: 0.24 seconds. Elapsed time: 0.54 seconds; current allocated memory: 163.119 MB.
INFO: [HLS 200-1510] Running: csynth_design
INFO: [HLS 200-111] Finished File checks and directory preparation: CPU user time: 0 seconds. CPU system time: 0 seconds. Elapsed time: 0.01 seconds; current allocated memory: 163.302 MB.
INFO: [HLS 200-10] Analyzing design file 'hls_example.cpp' ...
INFO: [HLS 200-111] Finished Source Code Analysis and Preprocessing: CPU user time: 1.52 seconds. CPU system time: 0.28 seconds. Elapsed time: 1.51 seconds; current allocated memory: 164.903 MB.
INFO: [HLS 200-1022] Execute customized passes: $LLVM_CUSTOM_OPT -load $::env(HLS_LLVM_PLUGIN_DIR)/LLVMCustomPasses.so -mem2reg -analyzer -renamer $LLVM_CUSTOM_INPUT -o $LLVM_CUSTOM_OUTPUT
LLVM_CUSTOM_OPT:/media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis_HLS/2020.2/lnx64/tools/clang-3.9-csynth/bin/opt
LLVM_CUSTOM_INPUT:/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/plugin_analyze_rename_flow_demo/proj/solution1/.autopilot/db/a.g.ld.5.gdce.bc
LLVM_CUSTOM_OUTPUT:/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/plugin_analyze_rename_flow_demo/proj/solution1/.autopilot/db/a.g.ld.6.user.bc
Loop at depth 1 containing: %2<header><exiting>,%3,%7<latch>
Backedge Taken Count: 50
II:1
%4 = load i32, i32* %arrayidx, align 4, !dbg !2252
Access Pattern: {%a,+,4}<%2> store i32 %4, i32* %arrayidx1, align 4, !dbg !2255
Access Pattern: {%buff,+,4}<%2> %5 = load i32, i32* %arrayidx2, align 4, !dbg !2256
Access Pattern: {%buff,+,4}<%2> store i32 %add, i32* %arrayidx3, align 4, !dbg !2259
Access Pattern: {%buff,+,4}<%2> %6 = load i32, i32* %arrayidx4, align 4, !dbg !2260
Access Pattern: {%buff,+,4}<%2> store i32 %6, i32* %arrayidx5, align 4, !dbg !2262
Access Pattern: {%b,+,4}<%2>INFO: [HLS 200-777] Using interface defaults for 'Vivado' flow target.
WARNING: [HLS 214-205] The INTERFACE pragma must have a max_widen_bitwidth setting that is both a power of 2 and in the range [0, 1024]. The current value of '0' will be ignored, in 'example(int*, int*)' (hls_example.cpp:27:0)
WARNING: [HLS 214-205] The INTERFACE pragma must have a max_widen_bitwidth setting that is both a power of 2 and in the range [0, 1024]. The current value of '0' will be ignored, in 'example(int*, int*)' (hls_example.cpp:27:0)
INFO: [HLS 214-115] Multiple burst reads of length 50 and bit width 32 in loop 'VITIS_LOOP_31_1'(hls_example.cpp:31:20) has been inferred on port 'aboba' (hls_example.cpp:31:20)
INFO: [HLS 214-115] Multiple burst writes of length 50 and bit width 32 in loop 'VITIS_LOOP_31_1'(hls_example.cpp:31:20) has been inferred on port 'bboba' (hls_example.cpp:31:20)
INFO: [HLS 200-111] Finished Compiling Optimization and Transform: CPU user time: 3.4 seconds. CPU system time: 0.29 seconds. Elapsed time: 3.73 seconds; current allocated memory: 165.954 MB.
INFO: [HLS 200-111] Finished Checking Pragmas: CPU user time: 0 seconds. CPU system time: 0 seconds. Elapsed time: 0 seconds; current allocated memory: 165.956 MB.
INFO: [HLS 200-10] Starting code transformations ...
INFO: [HLS 200-111] Finished Standard Transforms: CPU user time: 0.01 seconds. CPU system time: 0 seconds. Elapsed time: 0.02 seconds; current allocated memory: 167.748 MB.
INFO: [HLS 200-10] Checking synthesizability ...
INFO: [HLS 200-111] Finished Checking Synthesizability: CPU user time: 0.02 seconds. CPU system time: 0 seconds. Elapsed time: 0.02 seconds; current allocated memory: 167.906 MB.
INFO: [HLS 200-111] Finished Loop, function and other optimizations: CPU user time: 0.06 seconds. CPU system time: 0 seconds. Elapsed time: 0.07 seconds; current allocated memory: 189.088 MB.
INFO: [HLS 200-111] Finished Architecture Synthesis: CPU user time: 0.04 seconds. CPU system time: 0 seconds. Elapsed time: 0.03 seconds; current allocated memory: 181.710 MB.
INFO: [HLS 200-10] Starting hardware synthesis ...
INFO: [HLS 200-10] Synthesizing 'example' ...
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-42] -- Implementing module 'example'
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [SCHED 204-11] Starting scheduling ...
INFO: [SCHED 204-61] Pipelining loop 'VITIS_LOOP_31_1'.
INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 5, loop 'VITIS_LOOP_31_1'
INFO: [SCHED 204-11] Finished scheduling.
INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.03 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.04 seconds; current allocated memory: 181.992 MB.
INFO: [BIND 205-100] Starting micro-architecture generation ...
INFO: [BIND 205-101] Performing variable lifetime analysis.
INFO: [BIND 205-101] Exploring resource sharing.
INFO: [BIND 205-101] Binding ...
INFO: [BIND 205-100] Finished micro-architecture generation.
INFO: [HLS 200-111] Finished Binding: CPU user time: 0.07 seconds. CPU system time: 0 seconds. Elapsed time: 0.07 seconds; current allocated memory: 182.178 MB.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-10] -- Generating RTL for module 'example'
INFO: [HLS 200-10] ----------------------------------------------------------------
WARNING: [RTGEN 206-101] Design contains AXI ports. Reset is fixed to synchronous and active low.
INFO: [RTGEN 206-500] Setting interface mode on port 'example/aboba' to 'm_axi'.
INFO: [RTGEN 206-500] Setting interface mode on port 'example/bboba' to 'm_axi'.
INFO: [RTGEN 206-500] Setting interface mode on function 'example' to 'ap_ctrl_hs'.
INFO: [RTGEN 206-100] Generating core module 'add_32ns_32ns_32_2_1': 1 instance(s).
INFO: [RTGEN 206-100] Generating core module 'add_6ns_6ns_6_1_1': 1 instance(s).
INFO: [RTGEN 206-100] Finished creating RTL model for 'example'.
INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.04 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.04 seconds; current allocated memory: 183.188 MB.
INFO: [RTMG 210-283] Generating pipelined adder/subtractor : 'example_add_32ns_32ns_32_2_1_Adder_1'
INFO: [HLS 200-111] Finished Generating all RTL models: CPU user time: 1.03 seconds. CPU system time: 0.01 seconds. Elapsed time: 1.05 seconds; current allocated memory: 191.482 MB.
INFO: [VHDL 208-304] Generating VHDL RTL for example.
INFO: [VLOG 209-307] Generating Verilog RTL for example.
INFO: [HLS 200-1603] Design has MAXI bursts and missed bursts, see Vitis HLS GUI synthesis summary report for detailed information.
INFO: [HLS 200-790] **** Loop Constraint Status: All loop constraints were satisfied.
INFO: [HLS 200-789] **** Estimated Fmax: 411.00 MHz
INFO: [HLS 200-111] Finished Command csynth_design CPU user time: 6.31 seconds. CPU system time: 0.6 seconds. Elapsed time: 6.69 seconds; current allocated memory: 192.086 MB.
INFO: [HLS 200-1510] Running: cosim_design
INFO: [COSIM 212-47] Using XSIM for RTL simulation.
INFO: [COSIM 212-14] Instrumenting C test bench ...
Build using "/media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis_HLS/2020.2/tps/lnx64/gcc-6.2.0/bin/g++"
Compiling hls_example.cpp_pre.cpp.tb.cpp
Compiling apatb_example.cpp
Compiling apatb_example_ir.ll
Generating cosim.tv.exe
INFO: [COSIM 212-302] Starting C TB testing ...
Test passed.
INFO: [COSIM 212-333] Generating C post check test bench ...
INFO: [COSIM 212-12] Generating RTL test bench ...
INFO: [COSIM 212-1] *** C/RTL co-simulation file generation completed. ***
INFO: [COSIM 212-323] Starting verilog simulation.
INFO: [COSIM 212-15] Starting XSIM ...
Vivado Simulator 2020.2
Copyright 1986-1999, 2001-2020 Xilinx, Inc. All Rights Reserved.
Running: /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vivado/2020.2/bin/unwrapped/lnx64.o/xelab xil_defaultlib.apatb_example_top glbl -prj example.prj -L smartconnect_v1_0 -L axi_protocol_checker_v1_1_12 -L axi_protocol_checker_v1_1_13 -L axis_protocol_checker_v1_1_11 -L axis_protocol_checker_v1_1_12 -L xil_defaultlib -L unisims_ver -L xpm -L floating_point_v7_0_18 -L floating_point_v7_1_11 --lib ieee_proposed=./ieee_proposed -s example
Multi-threading is on. Using 2 slave threads.
WARNING: [XSIM 43-3431] One or more environment variables have been detected which affect the operation of the C compiler. These are typically not set in standard installations and are not tested by Xilinx, however they may be appropriate for your system, so the flow will attempt to continue. If errors occur, try running xelab with the "-mt off -v 1" switches to see more information from the C compiler. The following environment variables have been detected:
C_INCLUDE_PATH
LIBRARY_PATH
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/plugin_analyze_rename_flow_demo/proj/solution1/sim/verilog/glbl.v" into library work
INFO: [VRFC 10-311] analyzing module glbl
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/plugin_analyze_rename_flow_demo/proj/solution1/sim/verilog/example_aboba_m_axi.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module example_aboba_m_axi
INFO: [VRFC 10-311] analyzing module example_aboba_m_axi_reg_slice
INFO: [VRFC 10-311] analyzing module example_aboba_m_axi_fifo
INFO: [VRFC 10-311] analyzing module example_aboba_m_axi_buffer
INFO: [VRFC 10-311] analyzing module example_aboba_m_axi_decoder
INFO: [VRFC 10-311] analyzing module example_aboba_m_axi_throttle
INFO: [VRFC 10-311] analyzing module example_aboba_m_axi_read
INFO: [VRFC 10-311] analyzing module example_aboba_m_axi_write
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/plugin_analyze_rename_flow_demo/proj/solution1/sim/verilog/AESL_axi_master_bboba.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AESL_axi_master_bboba
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/plugin_analyze_rename_flow_demo/proj/solution1/sim/verilog/example_add_32ns_32ns_32_2_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module example_add_32ns_32ns_32_2_1_Adder_1
INFO: [VRFC 10-311] analyzing module example_add_32ns_32ns_32_2_1_Adder_1_comb_adder
INFO: [VRFC 10-311] analyzing module example_add_32ns_32ns_32_2_1
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/plugin_analyze_rename_flow_demo/proj/solution1/sim/verilog/example.autotb.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module apatb_example_top
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/plugin_analyze_rename_flow_demo/proj/solution1/sim/verilog/example_bboba_m_axi.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module example_bboba_m_axi
INFO: [VRFC 10-311] analyzing module example_bboba_m_axi_reg_slice
INFO: [VRFC 10-311] analyzing module example_bboba_m_axi_fifo
INFO: [VRFC 10-311] analyzing module example_bboba_m_axi_buffer
INFO: [VRFC 10-311] analyzing module example_bboba_m_axi_decoder
INFO: [VRFC 10-311] analyzing module example_bboba_m_axi_throttle
INFO: [VRFC 10-311] analyzing module example_bboba_m_axi_read
INFO: [VRFC 10-311] analyzing module example_bboba_m_axi_write
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/plugin_analyze_rename_flow_demo/proj/solution1/sim/verilog/example.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module example
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/plugin_analyze_rename_flow_demo/proj/solution1/sim/verilog/AESL_axi_master_aboba.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AESL_axi_master_aboba
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/plugin_analyze_rename_flow_demo/proj/solution1/sim/verilog/example_add_6ns_6ns_6_1_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module example_add_6ns_6ns_6_1_1_Adder_0
INFO: [VRFC 10-311] analyzing module example_add_6ns_6ns_6_1_1
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/plugin_analyze_rename_flow_demo/proj/solution1/sim/verilog/sample_manager.sv" into library xil_defaultlib
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/plugin_analyze_rename_flow_demo/proj/solution1/sim/verilog/sample_agent.sv" into library xil_defaultlib
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/plugin_analyze_rename_flow_demo/proj/solution1/sim/verilog/df_fifo_interface.sv" into library xil_defaultlib
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/plugin_analyze_rename_flow_demo/proj/solution1/sim/verilog/dump_file_agent.sv" into library xil_defaultlib
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/plugin_analyze_rename_flow_demo/proj/solution1/sim/verilog/nodf_module_monitor.sv" into library xil_defaultlib
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/plugin_analyze_rename_flow_demo/proj/solution1/sim/verilog/df_process_interface.sv" into library xil_defaultlib
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/plugin_analyze_rename_flow_demo/proj/solution1/sim/verilog/dataflow_monitor.sv" into library xil_defaultlib
WARNING: [VRFC 10-3609] overwriting previous definition of interface 'df_fifo_intf' [df_fifo_interface.sv:4]
WARNING: [VRFC 10-3609] overwriting previous definition of interface 'df_process_intf' [df_process_interface.sv:4]
WARNING: [VRFC 10-3609] overwriting previous definition of interface 'nodf_module_intf' [nodf_module_interface.sv:4]
INFO: [VRFC 10-311] analyzing module dataflow_monitor
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/plugin_analyze_rename_flow_demo/proj/solution1/sim/verilog/csv_file_dump.sv" into library xil_defaultlib
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/plugin_analyze_rename_flow_demo/proj/solution1/sim/verilog/nodf_module_interface.sv" into library xil_defaultlib
WARNING: [VRFC 10-3609] overwriting previous definition of interface 'nodf_module_intf' [/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/plugin_analyze_rename_flow_demo/proj/solution1/sim/verilog/nodf_module_interface.sv:4]
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/plugin_analyze_rename_flow_demo/proj/solution1/sim/verilog/df_process_monitor.sv" into library xil_defaultlib
WARNING: [VRFC 10-3609] overwriting previous definition of interface 'df_process_intf' [df_process_interface.sv:4]
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/plugin_analyze_rename_flow_demo/proj/solution1/sim/verilog/df_fifo_monitor.sv" into library xil_defaultlib
WARNING: [VRFC 10-3609] overwriting previous definition of interface 'df_fifo_intf' [df_fifo_interface.sv:4]
Starting static elaboration
Pass Through NonSizing Optimizer
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package xil_defaultlib.$unit_dataflow_monitor_sv
Compiling module xil_defaultlib.example_aboba_m_axi_reg_slice(N=...
Compiling module xil_defaultlib.example_aboba_m_axi_fifo(DATA_BI...
Compiling module xil_defaultlib.example_aboba_m_axi_buffer(DATA_...
Compiling module xil_defaultlib.example_aboba_m_axi_fifo(DEPTH=5...
Compiling module xil_defaultlib.example_aboba_m_axi_fifo(DATA_BI...
Compiling module xil_defaultlib.example_aboba_m_axi_fifo(DATA_BI...
Compiling module xil_defaultlib.example_aboba_m_axi_write(NUM_WR...
Compiling module xil_defaultlib.example_aboba_m_axi_buffer(DATA_...
Compiling module xil_defaultlib.example_aboba_m_axi_reg_slice(N=...
Compiling module xil_defaultlib.example_aboba_m_axi_read(NUM_REA...
Compiling module xil_defaultlib.example_aboba_m_axi_throttle(ADD...
Compiling module xil_defaultlib.example_aboba_m_axi(NUM_READ_OUT...
Compiling module xil_defaultlib.example_bboba_m_axi_reg_slice(N=...
Compiling module xil_defaultlib.example_bboba_m_axi_fifo(DATA_BI...
Compiling module xil_defaultlib.example_bboba_m_axi_buffer(DATA_...
Compiling module xil_defaultlib.example_bboba_m_axi_fifo(DEPTH=5...
Compiling module xil_defaultlib.example_bboba_m_axi_fifo(DATA_BI...
Compiling module xil_defaultlib.example_bboba_m_axi_fifo(DATA_BI...
Compiling module xil_defaultlib.example_bboba_m_axi_write(NUM_WR...
Compiling module xil_defaultlib.example_bboba_m_axi_buffer(DATA_...
Compiling module xil_defaultlib.example_bboba_m_axi_reg_slice(N=...
Compiling module xil_defaultlib.example_bboba_m_axi_read(NUM_REA...
Compiling module xil_defaultlib.example_bboba_m_axi_throttle(ADD...
Compiling module xil_defaultlib.example_bboba_m_axi(NUM_READ_OUT...
Compiling module xil_defaultlib.example_add_6ns_6ns_6_1_1_Adder_...
Compiling module xil_defaultlib.example_add_6ns_6ns_6_1_1(ID=1,N...
Compiling module xil_defaultlib.example_add_32ns_32ns_32_2_1_Add...
Compiling module xil_defaultlib.example_add_32ns_32ns_32_2_1_Add...
Compiling module xil_defaultlib.example_add_32ns_32ns_32_2_1(ID=...
Compiling module xil_defaultlib.example
Compiling module xil_defaultlib.AESL_axi_master_aboba
Compiling module xil_defaultlib.AESL_axi_master_bboba
Compiling module xil_defaultlib.nodf_module_intf
Compiling module xil_defaultlib.dataflow_monitor_1
Compiling module xil_defaultlib.apatb_example_top
Compiling module work.glbl
Built simulation snapshot example
****** Webtalk v2020.2 (64-bit)
**** SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
**** IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020
** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
source /media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/plugin_analyze_rename_flow_demo/proj/solution1/sim/verilog/xsim.dir/example/webtalk/xsim_webtalk.tcl -notrace
INFO: [Common 17-206] Exiting Webtalk at Fri Mar 12 03:53:47 2021...
****** xsim v2020.2 (64-bit)
**** SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
**** IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020
** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
source xsim.dir/example/xsim_script.tcl
# xsim {example} -autoloadwcfg -tclbatch {example.tcl}
Vivado Simulator 2020.2
Time resolution is 1 ps
source example.tcl
## run all
////////////////////////////////////////////////////////////////////////////////////
// Inter-Transaction Progress: Completed Transaction / Total Transaction
// Intra-Transaction Progress: Measured Latency / Latency Estimation * 100%
//
// RTL Simulation : "Inter-Transaction Progress" ["Intra-Transaction Progress"] @ "Simulation Time"
////////////////////////////////////////////////////////////////////////////////////
// RTL Simulation : 0 / 1 [0.00%] @ "109000"
// RTL Simulation : 1 / 1 [100.00%] @ "362000"
////////////////////////////////////////////////////////////////////////////////////
$finish called at time : 375750 ps : File "/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/plugin_analyze_rename_flow_demo/proj/solution1/sim/verilog/example.autotb.v" Line 462
## quit
INFO: [Common 17-206] Exiting xsim at Fri Mar 12 03:53:57 2021...
INFO: [COSIM 212-316] Starting C post checking ...
Test passed.
INFO: [COSIM 212-1000] *** C/RTL co-simulation finished: PASS ***
INFO: [COSIM 212-211] II is measurable only when transaction number is greater than 1 in RTL simulation. Otherwise, they will be marked as all NA. If user wants to calculate them, please make sure there are at least 2 transactions in RTL simulation.
INFO: [HLS 200-111] Finished Command cosim_design CPU user time: 23.04 seconds. CPU system time: 1.37 seconds. Elapsed time: 22.85 seconds; current allocated memory: 196.223 MB.
INFO: [HLS 200-112] Total CPU user time: 32.18 seconds. Total CPU system time: 2.64 seconds. Total elapsed time: 32.14 seconds; peak allocated memory: 191.482 MB.
INFO: [Common 17-206] Exiting vitis_hls at Fri Mar 12 03:53:57 2021...
masaaki@masaaki-H110M4-M01:/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/plugin_analyze_rename_flow_demo$
INFO: [HLS 200-1022] Execute customized passes: $LLVM_CUSTOM_OPT -load $::env(HLS_LLVM_PLUGIN_DIR)/LLVMCustomPasses.so -mem2reg -analyzer -renamer $LLVM_CUSTOM_INPUT -o $LLVM_CUSTOM_OUTPUT
LLVM_CUSTOM_OPT:/media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis_HLS/2020.2/lnx64/tools/clang-3.9-csynth/bin/opt
LLVM_CUSTOM_INPUT:/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/plugin_analyze_rename_flow_demo/proj/solution1/.autopilot/db/a.g.ld.5.gdce.bc
LLVM_CUSTOM_OUTPUT:/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/plugin_analyze_rename_flow_demo/proj/solution1/.autopilot/db/a.g.ld.6.user.bc
Loop at depth 1 containing: %2<header><exiting>,%3,%7<latch>
Backedge Taken Count: 50
II:1
%4 = load i32, i32* %arrayidx, align 4, !dbg !2252
Access Pattern: {%a,+,4}<%2> store i32 %4, i32* %arrayidx1, align 4, !dbg !2255
Access Pattern: {%buff,+,4}<%2> %5 = load i32, i32* %arrayidx2, align 4, !dbg !2256
Access Pattern: {%buff,+,4}<%2> store i32 %add, i32* %arrayidx3, align 4, !dbg !2259
Access Pattern: {%buff,+,4}<%2> %6 = load i32, i32* %arrayidx4, align 4, !dbg !2260
Access Pattern: {%buff,+,4}<%2> store i32 %6, i32* %arrayidx5, align 4, !dbg !2262
Access Pattern: {%b,+,4}<%2>INFO: [HLS 200-777] Using interface defaults for 'Vivado' flow target.
VitisHLS内でカスタムLLVMオプトパスを呼び出す方法。plugins / example_analyze_renameをビルドする必要があります。ローカルのLLVMビルドは必要ありません。
if { ![info exists ::env(HLS_LLVM_PLUGIN_DIR)] } {
# Use plugin example directory as default build directory
set ::env(HLS_LLVM_PLUGIN_DIR) [file normalize ../../plugins/example_analyze_rename]
}
if { ![file exists $::env(HLS_LLVM_PLUGIN_DIR)/LLVMCustomPasses.so] } {
error "Must build LLVMCustomPasses.so before running this example"
}
### The following variable must be set before csynth_design
# Do not use global namespace (::) for variables used in LVM_CUSTOM_CMD
set ::LLVM_CUSTOM_CMD {$LLVM_CUSTOM_OPT -load $::env(HLS_LLVM_PLUGIN_DIR)/LLVMCustomPasses.so -mem2reg -analyzer -renamer $LLVM_CUSTOM_INPUT -o $LLVM_CUSTOM_OUTPUT}
masaaki@masaaki-H110M4-M01:/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/plugin_analyze_rename_flow_demo$ vitis_hls run_hls.tcl
****** Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit)
**** SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
**** IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020
** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
source /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis_HLS/2020.2/scripts/vitis_hls/hls.tcl -notrace
INFO: [HLS 200-10] Running '/media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis_HLS/2020.2/bin/unwrapped/lnx64.o/vitis_hls'
INFO: [HLS 200-10] For user 'masaaki' on host 'masaaki-H110M4-M01' (Linux_x86_64 version 4.15.0-136-generic) on Fri Mar 12 03:53:25 JST 2021
INFO: [HLS 200-10] On os Ubuntu 18.04.5 LTS
INFO: [HLS 200-10] In directory '/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/plugin_analyze_rename_flow_demo'
WARNING: [HLS 200-40] Environment variable 'C_INCLUDE_PATH' is set to :/usr/local/cuda/include.
Sourcing Tcl script 'run_hls.tcl'
INFO: [HLS 200-1510] Running: open_project -reset proj
INFO: [HLS 200-10] Creating and opening project '/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/plugin_analyze_rename_flow_demo/proj'.
INFO: [HLS 200-1510] Running: add_files hls_example.cpp
INFO: [HLS 200-10] Adding design file 'hls_example.cpp' to the project
INFO: [HLS 200-1510] Running: add_files -tb hls_example.cpp
INFO: [HLS 200-10] Adding test bench file 'hls_example.cpp' to the project
INFO: [HLS 200-1510] Running: set_top example
INFO: [HLS 200-1510] Running: open_solution -reset solution1
INFO: [HLS 200-10] Creating and opening solution '/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/plugin_analyze_rename_flow_demo/proj/solution1'.
INFO: [HLS 200-10] Cleaning up the solution database.
WARNING: [HLS 200-40] No /media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/plugin_analyze_rename_flow_demo/proj/solution1/solution1.aps file found.
INFO: [HLS 200-1505] Using default flow_target 'vivado'
Resolution: For help on HLS 200-1505 see www.xilinx.com/cgi-bin/docs/rdoc?v=2020.2;t=hls+guidance;d=200-1505.html
INFO: [HLS 200-1510] Running: set_part artix7
INFO: [HLS 200-10] Setting target device to 'xc7a12ti-csg325-1L'
INFO: [HLS 200-1510] Running: create_clock -period 300MHz
INFO: [SYN 201-201] Setting up clock 'default' with a period of 3.333ns.
INFO: [HLS 200-1510] Running: csim_design
INFO: [SIM 211-2] *************** CSIM start ***************
INFO: [SIM 211-4] CSIM will launch GCC as the compiler.
Compiling ../../../../hls_example.cpp in debug mode
Generating csim.exe
Test passed.
INFO: [SIM 211-1] CSim done with 0 errors.
INFO: [SIM 211-3] *************** CSIM finish ***************
INFO: [HLS 200-111] Finished Command csim_design CPU user time: 0.84 seconds. CPU system time: 0.24 seconds. Elapsed time: 0.54 seconds; current allocated memory: 163.119 MB.
INFO: [HLS 200-1510] Running: csynth_design
INFO: [HLS 200-111] Finished File checks and directory preparation: CPU user time: 0 seconds. CPU system time: 0 seconds. Elapsed time: 0.01 seconds; current allocated memory: 163.302 MB.
INFO: [HLS 200-10] Analyzing design file 'hls_example.cpp' ...
INFO: [HLS 200-111] Finished Source Code Analysis and Preprocessing: CPU user time: 1.52 seconds. CPU system time: 0.28 seconds. Elapsed time: 1.51 seconds; current allocated memory: 164.903 MB.
INFO: [HLS 200-1022] Execute customized passes: $LLVM_CUSTOM_OPT -load $::env(HLS_LLVM_PLUGIN_DIR)/LLVMCustomPasses.so -mem2reg -analyzer -renamer $LLVM_CUSTOM_INPUT -o $LLVM_CUSTOM_OUTPUT
LLVM_CUSTOM_OPT:/media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis_HLS/2020.2/lnx64/tools/clang-3.9-csynth/bin/opt
LLVM_CUSTOM_INPUT:/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/plugin_analyze_rename_flow_demo/proj/solution1/.autopilot/db/a.g.ld.5.gdce.bc
LLVM_CUSTOM_OUTPUT:/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/plugin_analyze_rename_flow_demo/proj/solution1/.autopilot/db/a.g.ld.6.user.bc
Loop at depth 1 containing: %2<header><exiting>,%3,%7<latch>
Backedge Taken Count: 50
II:1
%4 = load i32, i32* %arrayidx, align 4, !dbg !2252
Access Pattern: {%a,+,4}<%2> store i32 %4, i32* %arrayidx1, align 4, !dbg !2255
Access Pattern: {%buff,+,4}<%2> %5 = load i32, i32* %arrayidx2, align 4, !dbg !2256
Access Pattern: {%buff,+,4}<%2> store i32 %add, i32* %arrayidx3, align 4, !dbg !2259
Access Pattern: {%buff,+,4}<%2> %6 = load i32, i32* %arrayidx4, align 4, !dbg !2260
Access Pattern: {%buff,+,4}<%2> store i32 %6, i32* %arrayidx5, align 4, !dbg !2262
Access Pattern: {%b,+,4}<%2>INFO: [HLS 200-777] Using interface defaults for 'Vivado' flow target.
WARNING: [HLS 214-205] The INTERFACE pragma must have a max_widen_bitwidth setting that is both a power of 2 and in the range [0, 1024]. The current value of '0' will be ignored, in 'example(int*, int*)' (hls_example.cpp:27:0)
WARNING: [HLS 214-205] The INTERFACE pragma must have a max_widen_bitwidth setting that is both a power of 2 and in the range [0, 1024]. The current value of '0' will be ignored, in 'example(int*, int*)' (hls_example.cpp:27:0)
INFO: [HLS 214-115] Multiple burst reads of length 50 and bit width 32 in loop 'VITIS_LOOP_31_1'(hls_example.cpp:31:20) has been inferred on port 'aboba' (hls_example.cpp:31:20)
INFO: [HLS 214-115] Multiple burst writes of length 50 and bit width 32 in loop 'VITIS_LOOP_31_1'(hls_example.cpp:31:20) has been inferred on port 'bboba' (hls_example.cpp:31:20)
INFO: [HLS 200-111] Finished Compiling Optimization and Transform: CPU user time: 3.4 seconds. CPU system time: 0.29 seconds. Elapsed time: 3.73 seconds; current allocated memory: 165.954 MB.
INFO: [HLS 200-111] Finished Checking Pragmas: CPU user time: 0 seconds. CPU system time: 0 seconds. Elapsed time: 0 seconds; current allocated memory: 165.956 MB.
INFO: [HLS 200-10] Starting code transformations ...
INFO: [HLS 200-111] Finished Standard Transforms: CPU user time: 0.01 seconds. CPU system time: 0 seconds. Elapsed time: 0.02 seconds; current allocated memory: 167.748 MB.
INFO: [HLS 200-10] Checking synthesizability ...
INFO: [HLS 200-111] Finished Checking Synthesizability: CPU user time: 0.02 seconds. CPU system time: 0 seconds. Elapsed time: 0.02 seconds; current allocated memory: 167.906 MB.
INFO: [HLS 200-111] Finished Loop, function and other optimizations: CPU user time: 0.06 seconds. CPU system time: 0 seconds. Elapsed time: 0.07 seconds; current allocated memory: 189.088 MB.
INFO: [HLS 200-111] Finished Architecture Synthesis: CPU user time: 0.04 seconds. CPU system time: 0 seconds. Elapsed time: 0.03 seconds; current allocated memory: 181.710 MB.
INFO: [HLS 200-10] Starting hardware synthesis ...
INFO: [HLS 200-10] Synthesizing 'example' ...
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-42] -- Implementing module 'example'
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [SCHED 204-11] Starting scheduling ...
INFO: [SCHED 204-61] Pipelining loop 'VITIS_LOOP_31_1'.
INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 5, loop 'VITIS_LOOP_31_1'
INFO: [SCHED 204-11] Finished scheduling.
INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.03 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.04 seconds; current allocated memory: 181.992 MB.
INFO: [BIND 205-100] Starting micro-architecture generation ...
INFO: [BIND 205-101] Performing variable lifetime analysis.
INFO: [BIND 205-101] Exploring resource sharing.
INFO: [BIND 205-101] Binding ...
INFO: [BIND 205-100] Finished micro-architecture generation.
INFO: [HLS 200-111] Finished Binding: CPU user time: 0.07 seconds. CPU system time: 0 seconds. Elapsed time: 0.07 seconds; current allocated memory: 182.178 MB.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-10] -- Generating RTL for module 'example'
INFO: [HLS 200-10] ----------------------------------------------------------------
WARNING: [RTGEN 206-101] Design contains AXI ports. Reset is fixed to synchronous and active low.
INFO: [RTGEN 206-500] Setting interface mode on port 'example/aboba' to 'm_axi'.
INFO: [RTGEN 206-500] Setting interface mode on port 'example/bboba' to 'm_axi'.
INFO: [RTGEN 206-500] Setting interface mode on function 'example' to 'ap_ctrl_hs'.
INFO: [RTGEN 206-100] Generating core module 'add_32ns_32ns_32_2_1': 1 instance(s).
INFO: [RTGEN 206-100] Generating core module 'add_6ns_6ns_6_1_1': 1 instance(s).
INFO: [RTGEN 206-100] Finished creating RTL model for 'example'.
INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.04 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.04 seconds; current allocated memory: 183.188 MB.
INFO: [RTMG 210-283] Generating pipelined adder/subtractor : 'example_add_32ns_32ns_32_2_1_Adder_1'
INFO: [HLS 200-111] Finished Generating all RTL models: CPU user time: 1.03 seconds. CPU system time: 0.01 seconds. Elapsed time: 1.05 seconds; current allocated memory: 191.482 MB.
INFO: [VHDL 208-304] Generating VHDL RTL for example.
INFO: [VLOG 209-307] Generating Verilog RTL for example.
INFO: [HLS 200-1603] Design has MAXI bursts and missed bursts, see Vitis HLS GUI synthesis summary report for detailed information.
INFO: [HLS 200-790] **** Loop Constraint Status: All loop constraints were satisfied.
INFO: [HLS 200-789] **** Estimated Fmax: 411.00 MHz
INFO: [HLS 200-111] Finished Command csynth_design CPU user time: 6.31 seconds. CPU system time: 0.6 seconds. Elapsed time: 6.69 seconds; current allocated memory: 192.086 MB.
INFO: [HLS 200-1510] Running: cosim_design
INFO: [COSIM 212-47] Using XSIM for RTL simulation.
INFO: [COSIM 212-14] Instrumenting C test bench ...
Build using "/media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis_HLS/2020.2/tps/lnx64/gcc-6.2.0/bin/g++"
Compiling hls_example.cpp_pre.cpp.tb.cpp
Compiling apatb_example.cpp
Compiling apatb_example_ir.ll
Generating cosim.tv.exe
INFO: [COSIM 212-302] Starting C TB testing ...
Test passed.
INFO: [COSIM 212-333] Generating C post check test bench ...
INFO: [COSIM 212-12] Generating RTL test bench ...
INFO: [COSIM 212-1] *** C/RTL co-simulation file generation completed. ***
INFO: [COSIM 212-323] Starting verilog simulation.
INFO: [COSIM 212-15] Starting XSIM ...
Vivado Simulator 2020.2
Copyright 1986-1999, 2001-2020 Xilinx, Inc. All Rights Reserved.
Running: /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vivado/2020.2/bin/unwrapped/lnx64.o/xelab xil_defaultlib.apatb_example_top glbl -prj example.prj -L smartconnect_v1_0 -L axi_protocol_checker_v1_1_12 -L axi_protocol_checker_v1_1_13 -L axis_protocol_checker_v1_1_11 -L axis_protocol_checker_v1_1_12 -L xil_defaultlib -L unisims_ver -L xpm -L floating_point_v7_0_18 -L floating_point_v7_1_11 --lib ieee_proposed=./ieee_proposed -s example
Multi-threading is on. Using 2 slave threads.
WARNING: [XSIM 43-3431] One or more environment variables have been detected which affect the operation of the C compiler. These are typically not set in standard installations and are not tested by Xilinx, however they may be appropriate for your system, so the flow will attempt to continue. If errors occur, try running xelab with the "-mt off -v 1" switches to see more information from the C compiler. The following environment variables have been detected:
C_INCLUDE_PATH
LIBRARY_PATH
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/plugin_analyze_rename_flow_demo/proj/solution1/sim/verilog/glbl.v" into library work
INFO: [VRFC 10-311] analyzing module glbl
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/plugin_analyze_rename_flow_demo/proj/solution1/sim/verilog/example_aboba_m_axi.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module example_aboba_m_axi
INFO: [VRFC 10-311] analyzing module example_aboba_m_axi_reg_slice
INFO: [VRFC 10-311] analyzing module example_aboba_m_axi_fifo
INFO: [VRFC 10-311] analyzing module example_aboba_m_axi_buffer
INFO: [VRFC 10-311] analyzing module example_aboba_m_axi_decoder
INFO: [VRFC 10-311] analyzing module example_aboba_m_axi_throttle
INFO: [VRFC 10-311] analyzing module example_aboba_m_axi_read
INFO: [VRFC 10-311] analyzing module example_aboba_m_axi_write
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/plugin_analyze_rename_flow_demo/proj/solution1/sim/verilog/AESL_axi_master_bboba.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AESL_axi_master_bboba
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/plugin_analyze_rename_flow_demo/proj/solution1/sim/verilog/example_add_32ns_32ns_32_2_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module example_add_32ns_32ns_32_2_1_Adder_1
INFO: [VRFC 10-311] analyzing module example_add_32ns_32ns_32_2_1_Adder_1_comb_adder
INFO: [VRFC 10-311] analyzing module example_add_32ns_32ns_32_2_1
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/plugin_analyze_rename_flow_demo/proj/solution1/sim/verilog/example.autotb.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module apatb_example_top
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/plugin_analyze_rename_flow_demo/proj/solution1/sim/verilog/example_bboba_m_axi.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module example_bboba_m_axi
INFO: [VRFC 10-311] analyzing module example_bboba_m_axi_reg_slice
INFO: [VRFC 10-311] analyzing module example_bboba_m_axi_fifo
INFO: [VRFC 10-311] analyzing module example_bboba_m_axi_buffer
INFO: [VRFC 10-311] analyzing module example_bboba_m_axi_decoder
INFO: [VRFC 10-311] analyzing module example_bboba_m_axi_throttle
INFO: [VRFC 10-311] analyzing module example_bboba_m_axi_read
INFO: [VRFC 10-311] analyzing module example_bboba_m_axi_write
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/plugin_analyze_rename_flow_demo/proj/solution1/sim/verilog/example.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module example
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/plugin_analyze_rename_flow_demo/proj/solution1/sim/verilog/AESL_axi_master_aboba.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AESL_axi_master_aboba
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/plugin_analyze_rename_flow_demo/proj/solution1/sim/verilog/example_add_6ns_6ns_6_1_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module example_add_6ns_6ns_6_1_1_Adder_0
INFO: [VRFC 10-311] analyzing module example_add_6ns_6ns_6_1_1
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/plugin_analyze_rename_flow_demo/proj/solution1/sim/verilog/sample_manager.sv" into library xil_defaultlib
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/plugin_analyze_rename_flow_demo/proj/solution1/sim/verilog/sample_agent.sv" into library xil_defaultlib
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/plugin_analyze_rename_flow_demo/proj/solution1/sim/verilog/df_fifo_interface.sv" into library xil_defaultlib
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/plugin_analyze_rename_flow_demo/proj/solution1/sim/verilog/dump_file_agent.sv" into library xil_defaultlib
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/plugin_analyze_rename_flow_demo/proj/solution1/sim/verilog/nodf_module_monitor.sv" into library xil_defaultlib
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/plugin_analyze_rename_flow_demo/proj/solution1/sim/verilog/df_process_interface.sv" into library xil_defaultlib
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/plugin_analyze_rename_flow_demo/proj/solution1/sim/verilog/dataflow_monitor.sv" into library xil_defaultlib
WARNING: [VRFC 10-3609] overwriting previous definition of interface 'df_fifo_intf' [df_fifo_interface.sv:4]
WARNING: [VRFC 10-3609] overwriting previous definition of interface 'df_process_intf' [df_process_interface.sv:4]
WARNING: [VRFC 10-3609] overwriting previous definition of interface 'nodf_module_intf' [nodf_module_interface.sv:4]
INFO: [VRFC 10-311] analyzing module dataflow_monitor
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/plugin_analyze_rename_flow_demo/proj/solution1/sim/verilog/csv_file_dump.sv" into library xil_defaultlib
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/plugin_analyze_rename_flow_demo/proj/solution1/sim/verilog/nodf_module_interface.sv" into library xil_defaultlib
WARNING: [VRFC 10-3609] overwriting previous definition of interface 'nodf_module_intf' [/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/plugin_analyze_rename_flow_demo/proj/solution1/sim/verilog/nodf_module_interface.sv:4]
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/plugin_analyze_rename_flow_demo/proj/solution1/sim/verilog/df_process_monitor.sv" into library xil_defaultlib
WARNING: [VRFC 10-3609] overwriting previous definition of interface 'df_process_intf' [df_process_interface.sv:4]
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/plugin_analyze_rename_flow_demo/proj/solution1/sim/verilog/df_fifo_monitor.sv" into library xil_defaultlib
WARNING: [VRFC 10-3609] overwriting previous definition of interface 'df_fifo_intf' [df_fifo_interface.sv:4]
Starting static elaboration
Pass Through NonSizing Optimizer
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package xil_defaultlib.$unit_dataflow_monitor_sv
Compiling module xil_defaultlib.example_aboba_m_axi_reg_slice(N=...
Compiling module xil_defaultlib.example_aboba_m_axi_fifo(DATA_BI...
Compiling module xil_defaultlib.example_aboba_m_axi_buffer(DATA_...
Compiling module xil_defaultlib.example_aboba_m_axi_fifo(DEPTH=5...
Compiling module xil_defaultlib.example_aboba_m_axi_fifo(DATA_BI...
Compiling module xil_defaultlib.example_aboba_m_axi_fifo(DATA_BI...
Compiling module xil_defaultlib.example_aboba_m_axi_write(NUM_WR...
Compiling module xil_defaultlib.example_aboba_m_axi_buffer(DATA_...
Compiling module xil_defaultlib.example_aboba_m_axi_reg_slice(N=...
Compiling module xil_defaultlib.example_aboba_m_axi_read(NUM_REA...
Compiling module xil_defaultlib.example_aboba_m_axi_throttle(ADD...
Compiling module xil_defaultlib.example_aboba_m_axi(NUM_READ_OUT...
Compiling module xil_defaultlib.example_bboba_m_axi_reg_slice(N=...
Compiling module xil_defaultlib.example_bboba_m_axi_fifo(DATA_BI...
Compiling module xil_defaultlib.example_bboba_m_axi_buffer(DATA_...
Compiling module xil_defaultlib.example_bboba_m_axi_fifo(DEPTH=5...
Compiling module xil_defaultlib.example_bboba_m_axi_fifo(DATA_BI...
Compiling module xil_defaultlib.example_bboba_m_axi_fifo(DATA_BI...
Compiling module xil_defaultlib.example_bboba_m_axi_write(NUM_WR...
Compiling module xil_defaultlib.example_bboba_m_axi_buffer(DATA_...
Compiling module xil_defaultlib.example_bboba_m_axi_reg_slice(N=...
Compiling module xil_defaultlib.example_bboba_m_axi_read(NUM_REA...
Compiling module xil_defaultlib.example_bboba_m_axi_throttle(ADD...
Compiling module xil_defaultlib.example_bboba_m_axi(NUM_READ_OUT...
Compiling module xil_defaultlib.example_add_6ns_6ns_6_1_1_Adder_...
Compiling module xil_defaultlib.example_add_6ns_6ns_6_1_1(ID=1,N...
Compiling module xil_defaultlib.example_add_32ns_32ns_32_2_1_Add...
Compiling module xil_defaultlib.example_add_32ns_32ns_32_2_1_Add...
Compiling module xil_defaultlib.example_add_32ns_32ns_32_2_1(ID=...
Compiling module xil_defaultlib.example
Compiling module xil_defaultlib.AESL_axi_master_aboba
Compiling module xil_defaultlib.AESL_axi_master_bboba
Compiling module xil_defaultlib.nodf_module_intf
Compiling module xil_defaultlib.dataflow_monitor_1
Compiling module xil_defaultlib.apatb_example_top
Compiling module work.glbl
Built simulation snapshot example
****** Webtalk v2020.2 (64-bit)
**** SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
**** IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020
** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
source /media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/plugin_analyze_rename_flow_demo/proj/solution1/sim/verilog/xsim.dir/example/webtalk/xsim_webtalk.tcl -notrace
INFO: [Common 17-206] Exiting Webtalk at Fri Mar 12 03:53:47 2021...
****** xsim v2020.2 (64-bit)
**** SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
**** IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020
** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
source xsim.dir/example/xsim_script.tcl
# xsim {example} -autoloadwcfg -tclbatch {example.tcl}
Vivado Simulator 2020.2
Time resolution is 1 ps
source example.tcl
## run all
////////////////////////////////////////////////////////////////////////////////////
// Inter-Transaction Progress: Completed Transaction / Total Transaction
// Intra-Transaction Progress: Measured Latency / Latency Estimation * 100%
//
// RTL Simulation : "Inter-Transaction Progress" ["Intra-Transaction Progress"] @ "Simulation Time"
////////////////////////////////////////////////////////////////////////////////////
// RTL Simulation : 0 / 1 [0.00%] @ "109000"
// RTL Simulation : 1 / 1 [100.00%] @ "362000"
////////////////////////////////////////////////////////////////////////////////////
$finish called at time : 375750 ps : File "/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/plugin_analyze_rename_flow_demo/proj/solution1/sim/verilog/example.autotb.v" Line 462
## quit
INFO: [Common 17-206] Exiting xsim at Fri Mar 12 03:53:57 2021...
INFO: [COSIM 212-316] Starting C post checking ...
Test passed.
INFO: [COSIM 212-1000] *** C/RTL co-simulation finished: PASS ***
INFO: [COSIM 212-211] II is measurable only when transaction number is greater than 1 in RTL simulation. Otherwise, they will be marked as all NA. If user wants to calculate them, please make sure there are at least 2 transactions in RTL simulation.
INFO: [HLS 200-111] Finished Command cosim_design CPU user time: 23.04 seconds. CPU system time: 1.37 seconds. Elapsed time: 22.85 seconds; current allocated memory: 196.223 MB.
INFO: [HLS 200-112] Total CPU user time: 32.18 seconds. Total CPU system time: 2.64 seconds. Total elapsed time: 32.14 seconds; peak allocated memory: 191.482 MB.
INFO: [Common 17-206] Exiting vitis_hls at Fri Mar 12 03:53:57 2021...
INFO: [HLS 200-1022] Execute customized passes: $LLVM_CUSTOM_OPT -load $::env(HLS_LLVM_PLUGIN_DIR)/LLVMCustomPasses.so -mem2reg -analyzer -renamer $LLVM_CUSTOM_INPUT -o $LLVM_CUSTOM_OUTPUT
LLVM_CUSTOM_OPT:/media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis_HLS/2020.2/lnx64/tools/clang-3.9-csynth/bin/opt
LLVM_CUSTOM_INPUT:/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/plugin_analyze_rename_flow_demo/proj/solution1/.autopilot/db/a.g.ld.5.gdce.bc
LLVM_CUSTOM_OUTPUT:/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/plugin_analyze_rename_flow_demo/proj/solution1/.autopilot/db/a.g.ld.6.user.bc
Loop at depth 1 containing: %2<header><exiting>,%3,%7<latch>
Backedge Taken Count: 50
II:1
%4 = load i32, i32* %arrayidx, align 4, !dbg !2252
Access Pattern: {%a,+,4}<%2> store i32 %4, i32* %arrayidx1, align 4, !dbg !2255
Access Pattern: {%buff,+,4}<%2> %5 = load i32, i32* %arrayidx2, align 4, !dbg !2256
Access Pattern: {%buff,+,4}<%2> store i32 %add, i32* %arrayidx3, align 4, !dbg !2259
Access Pattern: {%buff,+,4}<%2> %6 = load i32, i32* %arrayidx4, align 4, !dbg !2260
Access Pattern: {%buff,+,4}<%2> store i32 %6, i32* %arrayidx5, align 4, !dbg !2262
Access Pattern: {%b,+,4}<%2>INFO: [HLS 200-777] Using interface defaults for 'Vivado' flow target.
VitisHLS内でローカルLLVMoptバイナリを使用する方法。
で、ローカルの LLVM opt を指定した。set ::LLVM_CUSTOM_OPT [pwd]/../../llvm/hls-build/bin/opt
で、$LLVM_CUSTOM_OPT でローカルの LLVM opt を指定し、$LLVM_CUSTOM_INPUT で入力bcファイルのファイルパスを指定し、 $LLVM_CUSTOM_OUTPUT で出力bcファイルのファイルパスを指定している。なお、set ::LLVM_CUSTOM_CMD {$LLVM_CUSTOM_OPT -mem2reg -dce $LLVM_CUSTOM_INPUT -o $LLVM_CUSTOM_OUTPUT}
とのことだ。LVM_CUSTOM_CMDで使用される変数にグローバル名前空間(::)を使用しないでください
masaaki@masaaki-H110M4-M01:/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/override_opt_flow_demo$ vitis_hls run_hls.tcl
****** Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit)
**** SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
**** IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020
** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
source /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis_HLS/2020.2/scripts/vitis_hls/hls.tcl -notrace
INFO: [HLS 200-10] Running '/media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis_HLS/2020.2/bin/unwrapped/lnx64.o/vitis_hls'
INFO: [HLS 200-10] For user 'masaaki' on host 'masaaki-H110M4-M01' (Linux_x86_64 version 4.15.0-136-generic) on Wed Mar 10 03:34:58 JST 2021
INFO: [HLS 200-10] On os Ubuntu 18.04.5 LTS
INFO: [HLS 200-10] In directory '/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/override_opt_flow_demo'
WARNING: [HLS 200-40] Environment variable 'C_INCLUDE_PATH' is set to :/usr/local/cuda/include.
Sourcing Tcl script 'run_hls.tcl'
INFO: [HLS 200-1510] Running: open_project -reset proj
INFO: [HLS 200-10] Creating and opening project '/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/override_opt_flow_demo/proj'.
INFO: [HLS 200-1510] Running: add_files hls_example.cpp
INFO: [HLS 200-10] Adding design file 'hls_example.cpp' to the project
INFO: [HLS 200-1510] Running: add_files -tb hls_example.cpp
INFO: [HLS 200-10] Adding test bench file 'hls_example.cpp' to the project
INFO: [HLS 200-1510] Running: set_top example
INFO: [HLS 200-1510] Running: open_solution -reset solution1
INFO: [HLS 200-10] Creating and opening solution '/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/override_opt_flow_demo/proj/solution1'.
INFO: [HLS 200-10] Cleaning up the solution database.
WARNING: [HLS 200-40] No /media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/override_opt_flow_demo/proj/solution1/solution1.aps file found.
INFO: [HLS 200-1505] Using default flow_target 'vivado'
Resolution: For help on HLS 200-1505 see www.xilinx.com/cgi-bin/docs/rdoc?v=2020.2;t=hls+guidance;d=200-1505.html
INFO: [HLS 200-1510] Running: set_part artix7
INFO: [HLS 200-10] Setting target device to 'xc7a12ti-csg325-1L'
INFO: [HLS 200-1510] Running: create_clock -period 300MHz
INFO: [SYN 201-201] Setting up clock 'default' with a period of 3.333ns.
INFO: [HLS 200-1510] Running: csim_design
INFO: [SIM 211-2] *************** CSIM start ***************
INFO: [SIM 211-4] CSIM will launch GCC as the compiler.
Compiling ../../../../hls_example.cpp in debug mode
Generating csim.exe
Test passed.
INFO: [SIM 211-1] CSim done with 0 errors.
INFO: [SIM 211-3] *************** CSIM finish ***************
INFO: [HLS 200-111] Finished Command csim_design CPU user time: 0.74 seconds. CPU system time: 0.19 seconds. Elapsed time: 0.46 seconds; current allocated memory: 163.116 MB.
INFO: [HLS 200-1510] Running: csynth_design
INFO: [HLS 200-111] Finished File checks and directory preparation: CPU user time: 0 seconds. CPU system time: 0 seconds. Elapsed time: 0.01 seconds; current allocated memory: 163.314 MB.
INFO: [HLS 200-10] Analyzing design file 'hls_example.cpp' ...
INFO: [HLS 200-111] Finished Source Code Analysis and Preprocessing: CPU user time: 1.65 seconds. CPU system time: 0.22 seconds. Elapsed time: 2.13 seconds; current allocated memory: 164.915 MB.
INFO: [HLS 200-1022] Execute customized passes: $LLVM_CUSTOM_OPT -mem2reg -dce $LLVM_CUSTOM_INPUT -o $LLVM_CUSTOM_OUTPUT
LLVM_CUSTOM_OPT:/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/override_opt_flow_demo/../../llvm/hls-build/bin/opt
LLVM_CUSTOM_INPUT:/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/override_opt_flow_demo/proj/solution1/.autopilot/db/a.g.ld.5.gdce.bc
LLVM_CUSTOM_OUTPUT:/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/override_opt_flow_demo/proj/solution1/.autopilot/db/a.g.ld.6.user.bc
INFO: [HLS 200-777] Using interface defaults for 'Vivado' flow target.
WARNING: [HLS 214-205] The INTERFACE pragma must have a max_widen_bitwidth setting that is both a power of 2 and in the range [0, 1024]. The current value of '0' will be ignored, in 'example(int*, int*)' (hls_example.cpp:27:0)
WARNING: [HLS 214-205] The INTERFACE pragma must have a max_widen_bitwidth setting that is both a power of 2 and in the range [0, 1024]. The current value of '0' will be ignored, in 'example(int*, int*)' (hls_example.cpp:27:0)
INFO: [HLS 214-115] Multiple burst reads of length 50 and bit width 32 in loop 'VITIS_LOOP_31_1'(hls_example.cpp:31:20) has been inferred on port 'a' (hls_example.cpp:31:20)
INFO: [HLS 214-115] Multiple burst writes of length 50 and bit width 32 in loop 'VITIS_LOOP_31_1'(hls_example.cpp:31:20) has been inferred on port 'b' (hls_example.cpp:31:20)
INFO: [HLS 200-111] Finished Compiling Optimization and Transform: CPU user time: 3.54 seconds. CPU system time: 0.3 seconds. Elapsed time: 5.1 seconds; current allocated memory: 165.936 MB.
INFO: [HLS 200-111] Finished Checking Pragmas: CPU user time: 0 seconds. CPU system time: 0 seconds. Elapsed time: 0 seconds; current allocated memory: 165.937 MB.
INFO: [HLS 200-10] Starting code transformations ...
INFO: [HLS 200-111] Finished Standard Transforms: CPU user time: 0.01 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.02 seconds; current allocated memory: 167.731 MB.
INFO: [HLS 200-10] Checking synthesizability ...
INFO: [HLS 200-111] Finished Checking Synthesizability: CPU user time: 0.02 seconds. CPU system time: 0 seconds. Elapsed time: 0.02 seconds; current allocated memory: 167.905 MB.
INFO: [HLS 200-111] Finished Loop, function and other optimizations: CPU user time: 0.06 seconds. CPU system time: 0 seconds. Elapsed time: 0.06 seconds; current allocated memory: 189.069 MB.
INFO: [HLS 200-111] Finished Architecture Synthesis: CPU user time: 0.03 seconds. CPU system time: 0 seconds. Elapsed time: 0.04 seconds; current allocated memory: 181.703 MB.
INFO: [HLS 200-10] Starting hardware synthesis ...
INFO: [HLS 200-10] Synthesizing 'example' ...
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-42] -- Implementing module 'example'
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [SCHED 204-11] Starting scheduling ...
INFO: [SCHED 204-61] Pipelining loop 'VITIS_LOOP_31_1'.
INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 5, loop 'VITIS_LOOP_31_1'
INFO: [SCHED 204-11] Finished scheduling.
INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.05 seconds. CPU system time: 0 seconds. Elapsed time: 0.04 seconds; current allocated memory: 181.970 MB.
INFO: [BIND 205-100] Starting micro-architecture generation ...
INFO: [BIND 205-101] Performing variable lifetime analysis.
INFO: [BIND 205-101] Exploring resource sharing.
INFO: [BIND 205-101] Binding ...
INFO: [BIND 205-100] Finished micro-architecture generation.
INFO: [HLS 200-111] Finished Binding: CPU user time: 0.07 seconds. CPU system time: 0 seconds. Elapsed time: 0.07 seconds; current allocated memory: 182.169 MB.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-10] -- Generating RTL for module 'example'
INFO: [HLS 200-10] ----------------------------------------------------------------
WARNING: [RTGEN 206-101] Design contains AXI ports. Reset is fixed to synchronous and active low.
INFO: [RTGEN 206-500] Setting interface mode on port 'example/a' to 'm_axi'.
INFO: [RTGEN 206-500] Setting interface mode on port 'example/b' to 'm_axi'.
INFO: [RTGEN 206-500] Setting interface mode on function 'example' to 'ap_ctrl_hs'.
INFO: [RTGEN 206-100] Generating core module 'add_32ns_32ns_32_2_1': 1 instance(s).
INFO: [RTGEN 206-100] Generating core module 'add_6ns_6ns_6_1_1': 1 instance(s).
INFO: [RTGEN 206-100] Finished creating RTL model for 'example'.
INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.03 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.04 seconds; current allocated memory: 183.140 MB.
INFO: [RTMG 210-283] Generating pipelined adder/subtractor : 'example_add_32ns_32ns_32_2_1_Adder_1'
INFO: [HLS 200-111] Finished Generating all RTL models: CPU user time: 1.01 seconds. CPU system time: 0.02 seconds. Elapsed time: 1.06 seconds; current allocated memory: 191.461 MB.
INFO: [VHDL 208-304] Generating VHDL RTL for example.
INFO: [VLOG 209-307] Generating Verilog RTL for example.
INFO: [HLS 200-1603] Design has MAXI bursts and missed bursts, see Vitis HLS GUI synthesis summary report for detailed information.
INFO: [HLS 200-790] **** Loop Constraint Status: All loop constraints were satisfied.
INFO: [HLS 200-789] **** Estimated Fmax: 411.00 MHz
INFO: [HLS 200-111] Finished Command csynth_design CPU user time: 6.56 seconds. CPU system time: 0.57 seconds. Elapsed time: 8.68 seconds; current allocated memory: 192.049 MB.
INFO: [HLS 200-1510] Running: cosim_design
INFO: [COSIM 212-47] Using XSIM for RTL simulation.
INFO: [COSIM 212-14] Instrumenting C test bench ...
Build using "/media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis_HLS/2020.2/tps/lnx64/gcc-6.2.0/bin/g++"
Compiling hls_example.cpp_pre.cpp.tb.cpp
Compiling apatb_example.cpp
Compiling apatb_example_ir.ll
Generating cosim.tv.exe
INFO: [COSIM 212-302] Starting C TB testing ...
Test passed.
INFO: [COSIM 212-333] Generating C post check test bench ...
INFO: [COSIM 212-12] Generating RTL test bench ...
INFO: [COSIM 212-1] *** C/RTL co-simulation file generation completed. ***
INFO: [COSIM 212-323] Starting verilog simulation.
INFO: [COSIM 212-15] Starting XSIM ...
Vivado Simulator 2020.2
Copyright 1986-1999, 2001-2020 Xilinx, Inc. All Rights Reserved.
Running: /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vivado/2020.2/bin/unwrapped/lnx64.o/xelab xil_defaultlib.apatb_example_top glbl -prj example.prj -L smartconnect_v1_0 -L axi_protocol_checker_v1_1_12 -L axi_protocol_checker_v1_1_13 -L axis_protocol_checker_v1_1_11 -L axis_protocol_checker_v1_1_12 -L xil_defaultlib -L unisims_ver -L xpm -L floating_point_v7_0_18 -L floating_point_v7_1_11 --lib ieee_proposed=./ieee_proposed -s example
Multi-threading is on. Using 2 slave threads.
WARNING: [XSIM 43-3431] One or more environment variables have been detected which affect the operation of the C compiler. These are typically not set in standard installations and are not tested by Xilinx, however they may be appropriate for your system, so the flow will attempt to continue. If errors occur, try running xelab with the "-mt off -v 1" switches to see more information from the C compiler. The following environment variables have been detected:
C_INCLUDE_PATH
LIBRARY_PATH
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/override_opt_flow_demo/proj/solution1/sim/verilog/glbl.v" into library work
INFO: [VRFC 10-311] analyzing module glbl
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/override_opt_flow_demo/proj/solution1/sim/verilog/AESL_axi_master_a.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AESL_axi_master_a
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/override_opt_flow_demo/proj/solution1/sim/verilog/example_b_m_axi.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module example_b_m_axi
INFO: [VRFC 10-311] analyzing module example_b_m_axi_reg_slice
INFO: [VRFC 10-311] analyzing module example_b_m_axi_fifo
INFO: [VRFC 10-311] analyzing module example_b_m_axi_buffer
INFO: [VRFC 10-311] analyzing module example_b_m_axi_decoder
INFO: [VRFC 10-311] analyzing module example_b_m_axi_throttle
INFO: [VRFC 10-311] analyzing module example_b_m_axi_read
INFO: [VRFC 10-311] analyzing module example_b_m_axi_write
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/override_opt_flow_demo/proj/solution1/sim/verilog/example_add_32ns_32ns_32_2_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module example_add_32ns_32ns_32_2_1_Adder_1
INFO: [VRFC 10-311] analyzing module example_add_32ns_32ns_32_2_1_Adder_1_comb_adder
INFO: [VRFC 10-311] analyzing module example_add_32ns_32ns_32_2_1
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/override_opt_flow_demo/proj/solution1/sim/verilog/example_a_m_axi.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module example_a_m_axi
INFO: [VRFC 10-311] analyzing module example_a_m_axi_reg_slice
INFO: [VRFC 10-311] analyzing module example_a_m_axi_fifo
INFO: [VRFC 10-311] analyzing module example_a_m_axi_buffer
INFO: [VRFC 10-311] analyzing module example_a_m_axi_decoder
INFO: [VRFC 10-311] analyzing module example_a_m_axi_throttle
INFO: [VRFC 10-311] analyzing module example_a_m_axi_read
INFO: [VRFC 10-311] analyzing module example_a_m_axi_write
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/override_opt_flow_demo/proj/solution1/sim/verilog/example.autotb.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module apatb_example_top
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/override_opt_flow_demo/proj/solution1/sim/verilog/example.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module example
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/override_opt_flow_demo/proj/solution1/sim/verilog/example_add_6ns_6ns_6_1_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module example_add_6ns_6ns_6_1_1_Adder_0
INFO: [VRFC 10-311] analyzing module example_add_6ns_6ns_6_1_1
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/override_opt_flow_demo/proj/solution1/sim/verilog/AESL_axi_master_b.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AESL_axi_master_b
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/override_opt_flow_demo/proj/solution1/sim/verilog/sample_manager.sv" into library xil_defaultlib
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/override_opt_flow_demo/proj/solution1/sim/verilog/sample_agent.sv" into library xil_defaultlib
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/override_opt_flow_demo/proj/solution1/sim/verilog/df_fifo_interface.sv" into library xil_defaultlib
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/override_opt_flow_demo/proj/solution1/sim/verilog/dump_file_agent.sv" into library xil_defaultlib
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/override_opt_flow_demo/proj/solution1/sim/verilog/nodf_module_monitor.sv" into library xil_defaultlib
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/override_opt_flow_demo/proj/solution1/sim/verilog/df_process_interface.sv" into library xil_defaultlib
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/override_opt_flow_demo/proj/solution1/sim/verilog/dataflow_monitor.sv" into library xil_defaultlib
WARNING: [VRFC 10-3609] overwriting previous definition of interface 'df_fifo_intf' [df_fifo_interface.sv:4]
WARNING: [VRFC 10-3609] overwriting previous definition of interface 'df_process_intf' [df_process_interface.sv:4]
WARNING: [VRFC 10-3609] overwriting previous definition of interface 'nodf_module_intf' [nodf_module_interface.sv:4]
INFO: [VRFC 10-311] analyzing module dataflow_monitor
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/override_opt_flow_demo/proj/solution1/sim/verilog/csv_file_dump.sv" into library xil_defaultlib
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/override_opt_flow_demo/proj/solution1/sim/verilog/nodf_module_interface.sv" into library xil_defaultlib
WARNING: [VRFC 10-3609] overwriting previous definition of interface 'nodf_module_intf' [/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/override_opt_flow_demo/proj/solution1/sim/verilog/nodf_module_interface.sv:4]
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/override_opt_flow_demo/proj/solution1/sim/verilog/df_process_monitor.sv" into library xil_defaultlib
WARNING: [VRFC 10-3609] overwriting previous definition of interface 'df_process_intf' [df_process_interface.sv:4]
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/override_opt_flow_demo/proj/solution1/sim/verilog/df_fifo_monitor.sv" into library xil_defaultlib
WARNING: [VRFC 10-3609] overwriting previous definition of interface 'df_fifo_intf' [df_fifo_interface.sv:4]
Starting static elaboration
Pass Through NonSizing Optimizer
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package xil_defaultlib.$unit_dataflow_monitor_sv
Compiling module xil_defaultlib.example_a_m_axi_reg_slice(N=96)
Compiling module xil_defaultlib.example_a_m_axi_fifo(DATA_BITS=9...
Compiling module xil_defaultlib.example_a_m_axi_buffer(DATA_WIDT...
Compiling module xil_defaultlib.example_a_m_axi_fifo(DEPTH=5,DEP...
Compiling module xil_defaultlib.example_a_m_axi_fifo(DATA_BITS=2...
Compiling module xil_defaultlib.example_a_m_axi_fifo(DATA_BITS=2...
Compiling module xil_defaultlib.example_a_m_axi_write(NUM_WRITE_...
Compiling module xil_defaultlib.example_a_m_axi_buffer(DATA_WIDT...
Compiling module xil_defaultlib.example_a_m_axi_reg_slice(N=34)
Compiling module xil_defaultlib.example_a_m_axi_read(NUM_READ_OU...
Compiling module xil_defaultlib.example_a_m_axi_throttle(ADDR_WI...
Compiling module xil_defaultlib.example_a_m_axi(NUM_READ_OUTSTAN...
Compiling module xil_defaultlib.example_b_m_axi_reg_slice(N=96)
Compiling module xil_defaultlib.example_b_m_axi_fifo(DATA_BITS=9...
Compiling module xil_defaultlib.example_b_m_axi_buffer(DATA_WIDT...
Compiling module xil_defaultlib.example_b_m_axi_fifo(DEPTH=5,DEP...
Compiling module xil_defaultlib.example_b_m_axi_fifo(DATA_BITS=2...
Compiling module xil_defaultlib.example_b_m_axi_fifo(DATA_BITS=2...
Compiling module xil_defaultlib.example_b_m_axi_write(NUM_WRITE_...
Compiling module xil_defaultlib.example_b_m_axi_buffer(DATA_WIDT...
Compiling module xil_defaultlib.example_b_m_axi_reg_slice(N=34)
Compiling module xil_defaultlib.example_b_m_axi_read(NUM_READ_OU...
Compiling module xil_defaultlib.example_b_m_axi_throttle(ADDR_WI...
Compiling module xil_defaultlib.example_b_m_axi(NUM_READ_OUTSTAN...
Compiling module xil_defaultlib.example_add_6ns_6ns_6_1_1_Adder_...
Compiling module xil_defaultlib.example_add_6ns_6ns_6_1_1(ID=1,N...
Compiling module xil_defaultlib.example_add_32ns_32ns_32_2_1_Add...
Compiling module xil_defaultlib.example_add_32ns_32ns_32_2_1_Add...
Compiling module xil_defaultlib.example_add_32ns_32ns_32_2_1(ID=...
Compiling module xil_defaultlib.example
Compiling module xil_defaultlib.AESL_axi_master_a
Compiling module xil_defaultlib.AESL_axi_master_b
Compiling module xil_defaultlib.nodf_module_intf
Compiling module xil_defaultlib.dataflow_monitor_1
Compiling module xil_defaultlib.apatb_example_top
Compiling module work.glbl
Built simulation snapshot example
****** Webtalk v2020.2 (64-bit)
**** SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
**** IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020
** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
source /media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/override_opt_flow_demo/proj/solution1/sim/verilog/xsim.dir/example/webtalk/xsim_webtalk.tcl -notrace
INFO: [Common 17-206] Exiting Webtalk at Wed Mar 10 03:35:22 2021...
****** xsim v2020.2 (64-bit)
**** SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
**** IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020
** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
source xsim.dir/example/xsim_script.tcl
# xsim {example} -autoloadwcfg -tclbatch {example.tcl}
Vivado Simulator 2020.2
Time resolution is 1 ps
source example.tcl
## run all
////////////////////////////////////////////////////////////////////////////////////
// Inter-Transaction Progress: Completed Transaction / Total Transaction
// Intra-Transaction Progress: Measured Latency / Latency Estimation * 100%
//
// RTL Simulation : "Inter-Transaction Progress" ["Intra-Transaction Progress"] @ "Simulation Time"
////////////////////////////////////////////////////////////////////////////////////
// RTL Simulation : 0 / 1 [0.00%] @ "109000"
// RTL Simulation : 1 / 1 [100.00%] @ "362000"
////////////////////////////////////////////////////////////////////////////////////
$finish called at time : 375750 ps : File "/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/override_opt_flow_demo/proj/solution1/sim/verilog/example.autotb.v" Line 462
## quit
INFO: [Common 17-206] Exiting xsim at Wed Mar 10 03:35:31 2021...
INFO: [COSIM 212-316] Starting C post checking ...
Test passed.
INFO: [COSIM 212-1000] *** C/RTL co-simulation finished: PASS ***
INFO: [COSIM 212-211] II is measurable only when transaction number is greater than 1 in RTL simulation. Otherwise, they will be marked as all NA. If user wants to calculate them, please make sure there are at least 2 transactions in RTL simulation.
INFO: [HLS 200-111] Finished Command cosim_design CPU user time: 22.84 seconds. CPU system time: 1.14 seconds. Elapsed time: 22.49 seconds; current allocated memory: 196.155 MB.
INFO: [HLS 200-112] Total CPU user time: 32.16 seconds. Total CPU system time: 2.33 seconds. Total elapsed time: 33.54 seconds; peak allocated memory: 191.461 MB.
INFO: [Common 17-206] Exiting vitis_hls at Wed Mar 10 03:35:32 2021...
Fosc/(16 * (n + 1)) = 32000000 / (16 * (3 + 1)) = 500000 bps = 500 kbps
// UART
BAUDCON = 0; // BRG16=0: 8bit counter mode
SPBRGL = 3; // SYNC=0, BRGH=1, BRG16=0, 500000bps
TXSTA = 0b00100100; // TXEN=1, SYNC=0, BRGH=1
RCSTA = 0b10010000; // SPEN=1, CREN=1
// USART 割り込みありの場合
RCIE = 1;
RCIF = 0;
PEIE = 1;
GIE = 1;
/* * File: acc3_uart.c * Author: ono * * Created on 2021/02/03, 11:09 */
#include <xc.h>
#pragma config FOSC = INTOSC
#pragma config LVP = OFF
#pragma config PWRTE = ON
unsigned char chr;
unsigned int n = 0;
void Delay(unsigned int m)
{
for(n=0;n<m;n++); //Delay
}
void main( void )
{
OSCCON = 0b11110000; // 4x PLL enable, 8MHz or 32MHz, FOSC
OSCTUNE = 0x00;
TRISA = 0;
TRISC = 0x23; // SCL, SDA, UART RX is input setting.
ANSELA = 0;
ANSELC = 0;
//I2C
SSP1ADD = 0x13; //speed 400KHz
SSP1STAT = 0b00000000; // 400kHz
SSP1CON1 = 0b00101000; //SSP1EN=1, Master mode
SSP1CON2 = 0b00000000;
// UART
BAUDCON = 0; // BRG16=0: 8bit counter mode
SPBRGL = 3; // SYNC=0, BRGH=1, BRG16=0, 500000bps
TXSTA = 0b00100100; // TXEN=1, SYNC=0, BRGH=1
RCSTA = 0b10010000; // SPEN=1, CREN=1
//INTCON = 0b11000000; // GIE=1, PEIE=1
while(1){
while(TRMT == 0);
TXREG = 0x55;
while(RCIF == 0);
RCIF = 0;
chr = RCREG;
//Delay(10);
while(TRMT == 0);
TXREG = chr + 1;
while(RCIF == 0);
RCIF = 0;
chr = RCREG;
Delay(50);
}
}
/* * File: acc3_uart.c * Author: ono * * Created on 2021/02/03, 11:09 */
#include <xc.h>
#pragma config FOSC = INTOSC
#pragma config LVP = OFF
#pragma config PWRTE = ON
unsigned char chr;
unsigned int n = 0;
void Delay(unsigned int m)
{
for(n=0;n<m;n++); //Delay
}
void main( void )
{
OSCCON = 0b11110000; // 4x PLL enable, 8MHz or 32MHz, FOSC
OSCTUNE = 0x00;
TRISA = 0;
TRISC = 0x23; // SCL, SDA, UART RX is input setting.
ANSELA = 0;
ANSELC = 0;
//I2C
SSP1ADD = 0x13; //speed 400KHz
SSP1STAT = 0b00000000; // 400kHz
SSP1CON1 = 0b00101000; //SSP1EN=1, Master mode
SSP1CON2 = 0b00000000;
// UART
BAUDCON = 0; // BRG16=0: 8bit counter mode
SPBRGL = 3; // SYNC=0, BRGH=1, BRG16=0, 500000bps
TXSTA = 0b00100100; // TXEN=1, SYNC=0, BRGH=1
RCSTA = 0b10010000; // SPEN=1, CREN=1
//INTCON = 0b11000000; // GIE=1, PEIE=1
RCIE = 1;
RCIF = 0;
PEIE = 1;
GIE = 1;
while(1){
while(TRMT == 0);
TXREG = 0x55;
Delay(50);
}
}
void interrupt RX_int(void){
if(RCIF == 1){
RCIF = 0;
chr = RCREG;
if(RCREG != 0x55)
return;
while(TRMT == 0);
TXREG = chr + 1;
}
}
”サヌキテックネットPICマイコン Lab.第4章 PICA Tower(ピカタワー)で学ぶ4-12.レジスターの設定”参照。#pragma config FOSC = INTOSC
OSCCON = 0b11110000; // 4x PLL enable, 8MHz or 32MHz, FOSC
OSCTUNE = 0x00;
ポートはAポートとCポートがある。TRISA = 0;
TRISC = 0x23; // SCL, SDA, UART RX is input setting.
ANSELA = 0;
ANSELC = 0;
それではやってみよう。”VitisHLS内でローカルLLVMビルドを使用する方法。ローカルLLVMは、clangフェーズとoptフェーズの両方に使用されます。”
masaaki@masaaki-H110M4-M01:/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/override_llvm_flow_demo$ vitis_hls run_hls.tcl
****** Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit)
**** SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
**** IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020
** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
source /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis_HLS/2020.2/scripts/vitis_hls/hls.tcl -notrace
INFO: [HLS 200-10] Running '/media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis_HLS/2020.2/bin/unwrapped/lnx64.o/vitis_hls'
INFO: [HLS 200-10] For user 'masaaki' on host 'masaaki-H110M4-M01' (Linux_x86_64 version 4.15.0-136-generic) on Tue Mar 09 20:31:58 JST 2021
INFO: [HLS 200-10] On os Ubuntu 18.04.5 LTS
INFO: [HLS 200-10] In directory '/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/override_llvm_flow_demo'
WARNING: [HLS 200-40] Environment variable 'C_INCLUDE_PATH' is set to :/usr/local/cuda/include.
Sourcing Tcl script 'run_hls.tcl'
INFO: [HLS 200-1510] Running: open_project -reset proj
INFO: [HLS 200-10] Creating and opening project '/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/override_llvm_flow_demo/proj'.
INFO: [HLS 200-1510] Running: add_files hls_example.cpp
INFO: [HLS 200-10] Adding design file 'hls_example.cpp' to the project
INFO: [HLS 200-1510] Running: add_files -tb hls_example.cpp
INFO: [HLS 200-10] Adding test bench file 'hls_example.cpp' to the project
INFO: [HLS 200-1510] Running: set_top example
INFO: [HLS 200-1510] Running: open_solution -reset solution1
INFO: [HLS 200-10] Creating and opening solution '/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/override_llvm_flow_demo/proj/solution1'.
INFO: [HLS 200-10] Cleaning up the solution database.
WARNING: [HLS 200-40] No /media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/override_llvm_flow_demo/proj/solution1/solution1.aps file found.
INFO: [HLS 200-1505] Using default flow_target 'vivado'
Resolution: For help on HLS 200-1505 see www.xilinx.com/cgi-bin/docs/rdoc?v=2020.2;t=hls+guidance;d=200-1505.html
INFO: [HLS 200-1510] Running: set_part artix7
INFO: [HLS 200-10] Setting target device to 'xc7a12ti-csg325-1L'
INFO: [HLS 200-1510] Running: create_clock -period 300MHz
INFO: [SYN 201-201] Setting up clock 'default' with a period of 3.333ns.
INFO: [HLS 200-1510] Running: csim_design
INFO: [SIM 211-2] *************** CSIM start ***************
INFO: [SIM 211-4] CSIM will launch GCC as the compiler.
Compiling ../../../../hls_example.cpp in debug mode
Generating csim.exe
Test passed.
INFO: [SIM 211-1] CSim done with 0 errors.
INFO: [SIM 211-3] *************** CSIM finish ***************
INFO: [HLS 200-111] Finished Command csim_design CPU user time: 0.44 seconds. CPU system time: 0.14 seconds. Elapsed time: 1.77 seconds; current allocated memory: 179.122 MB.
INFO: [HLS 200-1510] Running: csynth_design
INFO: [HLS 200-111] Finished File checks and directory preparation: CPU user time: 0 seconds. CPU system time: 0 seconds. Elapsed time: 0.01 seconds; current allocated memory: 179.289 MB.
INFO: [HLS 200-10] Analyzing design file 'hls_example.cpp' ...
INFO: [HLS 200-111] Finished Source Code Analysis and Preprocessing: CPU user time: 19.15 seconds. CPU system time: 0.4 seconds. Elapsed time: 24.69 seconds; current allocated memory: 180.886 MB.
INFO: [HLS 200-777] Using interface defaults for 'Vivado' flow target.
WARNING: [HLS 207-586] overriding the module target triple with fpga64-xilinx-none
WARNING: [HLS 214-205] The INTERFACE pragma must have a max_widen_bitwidth setting that is both a power of 2 and in the range [0, 1024]. The current value of '0' will be ignored, in 'example(int*, int*)' (hls_example.cpp:27:0)
WARNING: [HLS 214-205] The INTERFACE pragma must have a max_widen_bitwidth setting that is both a power of 2 and in the range [0, 1024]. The current value of '0' will be ignored, in 'example(int*, int*)' (hls_example.cpp:27:0)
INFO: [HLS 214-115] Multiple burst reads of length 50 and bit width 32 in loop 'VITIS_LOOP_31_1'(hls_example.cpp:31:20) has been inferred on port 'a' (hls_example.cpp:31:20)
INFO: [HLS 214-115] Multiple burst writes of length 50 and bit width 32 in loop 'VITIS_LOOP_31_1'(hls_example.cpp:31:20) has been inferred on port 'b' (hls_example.cpp:31:20)
INFO: [HLS 200-111] Finished Compiling Optimization and Transform: CPU user time: 3.51 seconds. CPU system time: 0.32 seconds. Elapsed time: 4.7 seconds; current allocated memory: 181.986 MB.
INFO: [HLS 200-111] Finished Checking Pragmas: CPU user time: 0 seconds. CPU system time: 0 seconds. Elapsed time: 0 seconds; current allocated memory: 181.987 MB.
INFO: [HLS 200-10] Starting code transformations ...
INFO: [HLS 200-111] Finished Standard Transforms: CPU user time: 0.06 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.45 seconds; current allocated memory: 183.780 MB.
INFO: [HLS 200-10] Checking synthesizability ...
INFO: [HLS 200-111] Finished Checking Synthesizability: CPU user time: 0.04 seconds. CPU system time: 0 seconds. Elapsed time: 0.07 seconds; current allocated memory: 183.954 MB.
INFO: [HLS 200-111] Finished Loop, function and other optimizations: CPU user time: 0.08 seconds. CPU system time: 0 seconds. Elapsed time: 0.08 seconds; current allocated memory: 205.119 MB.
INFO: [HLS 200-111] Finished Architecture Synthesis: CPU user time: 0.05 seconds. CPU system time: 0 seconds. Elapsed time: 0.08 seconds; current allocated memory: 197.771 MB.
INFO: [HLS 200-10] Starting hardware synthesis ...
INFO: [HLS 200-10] Synthesizing 'example' ...
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-42] -- Implementing module 'example'
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [SCHED 204-11] Starting scheduling ...
INFO: [SCHED 204-61] Pipelining loop 'VITIS_LOOP_31_1'.
INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 5, loop 'VITIS_LOOP_31_1'
INFO: [SCHED 204-11] Finished scheduling.
INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.08 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.15 seconds; current allocated memory: 198.036 MB.
INFO: [BIND 205-100] Starting micro-architecture generation ...
INFO: [BIND 205-101] Performing variable lifetime analysis.
INFO: [BIND 205-101] Exploring resource sharing.
INFO: [BIND 205-101] Binding ...
INFO: [BIND 205-100] Finished micro-architecture generation.
INFO: [HLS 200-111] Finished Binding: CPU user time: 0.08 seconds. CPU system time: 0 seconds. Elapsed time: 0.09 seconds; current allocated memory: 198.209 MB.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-10] -- Generating RTL for module 'example'
INFO: [HLS 200-10] ----------------------------------------------------------------
WARNING: [RTGEN 206-101] Design contains AXI ports. Reset is fixed to synchronous and active low.
INFO: [RTGEN 206-500] Setting interface mode on port 'example/a' to 'm_axi'.
INFO: [RTGEN 206-500] Setting interface mode on port 'example/b' to 'm_axi'.
INFO: [RTGEN 206-500] Setting interface mode on function 'example' to 'ap_ctrl_hs'.
INFO: [RTGEN 206-100] Generating core module 'add_32ns_32ns_32_2_1': 1 instance(s).
INFO: [RTGEN 206-100] Generating core module 'add_6ns_6ns_6_1_1': 1 instance(s).
INFO: [RTGEN 206-100] Finished creating RTL model for 'example'.
INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.04 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.07 seconds; current allocated memory: 199.179 MB.
INFO: [RTMG 210-283] Generating pipelined adder/subtractor : 'example_add_32ns_32ns_32_2_1_Adder_1'
INFO: [HLS 200-111] Finished Generating all RTL models: CPU user time: 1.07 seconds. CPU system time: 0.03 seconds. Elapsed time: 1.3 seconds; current allocated memory: 207.484 MB.
INFO: [VHDL 208-304] Generating VHDL RTL for example.
INFO: [VLOG 209-307] Generating Verilog RTL for example.
INFO: [HLS 200-1603] Design has MAXI bursts and missed bursts, see Vitis HLS GUI synthesis summary report for detailed information.
INFO: [HLS 200-790] **** Loop Constraint Status: All loop constraints were satisfied.
INFO: [HLS 200-789] **** Estimated Fmax: 411.00 MHz
INFO: [HLS 200-111] Finished Command csynth_design CPU user time: 24.25 seconds. CPU system time: 0.78 seconds. Elapsed time: 31.77 seconds; current allocated memory: 208.072 MB.
INFO: [HLS 200-1510] Running: cosim_design
INFO: [COSIM 212-47] Using XSIM for RTL simulation.
INFO: [COSIM 212-14] Instrumenting C test bench ...
Build using "/media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis_HLS/2020.2/tps/lnx64/gcc-6.2.0/bin/g++"
Compiling hls_example.cpp_pre.cpp.tb.cpp
Compiling apatb_example.cpp
Compiling apatb_example_ir.ll
Generating cosim.tv.exe
INFO: [COSIM 212-302] Starting C TB testing ...
Test passed.
INFO: [COSIM 212-333] Generating C post check test bench ...
INFO: [COSIM 212-12] Generating RTL test bench ...
INFO: [COSIM 212-1] *** C/RTL co-simulation file generation completed. ***
INFO: [COSIM 212-323] Starting verilog simulation.
INFO: [COSIM 212-15] Starting XSIM ...
Vivado Simulator 2020.2
Copyright 1986-1999, 2001-2020 Xilinx, Inc. All Rights Reserved.
Running: /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vivado/2020.2/bin/unwrapped/lnx64.o/xelab xil_defaultlib.apatb_example_top glbl -prj example.prj -L smartconnect_v1_0 -L axi_protocol_checker_v1_1_12 -L axi_protocol_checker_v1_1_13 -L axis_protocol_checker_v1_1_11 -L axis_protocol_checker_v1_1_12 -L xil_defaultlib -L unisims_ver -L xpm -L floating_point_v7_0_18 -L floating_point_v7_1_11 --lib ieee_proposed=./ieee_proposed -s example
Multi-threading is on. Using 2 slave threads.
WARNING: [XSIM 43-3431] One or more environment variables have been detected which affect the operation of the C compiler. These are typically not set in standard installations and are not tested by Xilinx, however they may be appropriate for your system, so the flow will attempt to continue. If errors occur, try running xelab with the "-mt off -v 1" switches to see more information from the C compiler. The following environment variables have been detected:
C_INCLUDE_PATH
LIBRARY_PATH
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/override_llvm_flow_demo/proj/solution1/sim/verilog/glbl.v" into library work
INFO: [VRFC 10-311] analyzing module glbl
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/override_llvm_flow_demo/proj/solution1/sim/verilog/AESL_axi_master_a.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AESL_axi_master_a
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/override_llvm_flow_demo/proj/solution1/sim/verilog/example_b_m_axi.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module example_b_m_axi
INFO: [VRFC 10-311] analyzing module example_b_m_axi_reg_slice
INFO: [VRFC 10-311] analyzing module example_b_m_axi_fifo
INFO: [VRFC 10-311] analyzing module example_b_m_axi_buffer
INFO: [VRFC 10-311] analyzing module example_b_m_axi_decoder
INFO: [VRFC 10-311] analyzing module example_b_m_axi_throttle
INFO: [VRFC 10-311] analyzing module example_b_m_axi_read
INFO: [VRFC 10-311] analyzing module example_b_m_axi_write
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/override_llvm_flow_demo/proj/solution1/sim/verilog/example_add_32ns_32ns_32_2_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module example_add_32ns_32ns_32_2_1_Adder_1
INFO: [VRFC 10-311] analyzing module example_add_32ns_32ns_32_2_1_Adder_1_comb_adder
INFO: [VRFC 10-311] analyzing module example_add_32ns_32ns_32_2_1
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/override_llvm_flow_demo/proj/solution1/sim/verilog/example_a_m_axi.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module example_a_m_axi
INFO: [VRFC 10-311] analyzing module example_a_m_axi_reg_slice
INFO: [VRFC 10-311] analyzing module example_a_m_axi_fifo
INFO: [VRFC 10-311] analyzing module example_a_m_axi_buffer
INFO: [VRFC 10-311] analyzing module example_a_m_axi_decoder
INFO: [VRFC 10-311] analyzing module example_a_m_axi_throttle
INFO: [VRFC 10-311] analyzing module example_a_m_axi_read
INFO: [VRFC 10-311] analyzing module example_a_m_axi_write
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/override_llvm_flow_demo/proj/solution1/sim/verilog/example.autotb.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module apatb_example_top
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/override_llvm_flow_demo/proj/solution1/sim/verilog/example.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module example
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/override_llvm_flow_demo/proj/solution1/sim/verilog/example_add_6ns_6ns_6_1_1.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module example_add_6ns_6ns_6_1_1_Adder_0
INFO: [VRFC 10-311] analyzing module example_add_6ns_6ns_6_1_1
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/override_llvm_flow_demo/proj/solution1/sim/verilog/AESL_axi_master_b.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AESL_axi_master_b
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/override_llvm_flow_demo/proj/solution1/sim/verilog/sample_manager.sv" into library xil_defaultlib
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/override_llvm_flow_demo/proj/solution1/sim/verilog/sample_agent.sv" into library xil_defaultlib
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/override_llvm_flow_demo/proj/solution1/sim/verilog/df_fifo_interface.sv" into library xil_defaultlib
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/override_llvm_flow_demo/proj/solution1/sim/verilog/dump_file_agent.sv" into library xil_defaultlib
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/override_llvm_flow_demo/proj/solution1/sim/verilog/nodf_module_monitor.sv" into library xil_defaultlib
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/override_llvm_flow_demo/proj/solution1/sim/verilog/df_process_interface.sv" into library xil_defaultlib
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/override_llvm_flow_demo/proj/solution1/sim/verilog/dataflow_monitor.sv" into library xil_defaultlib
WARNING: [VRFC 10-3609] overwriting previous definition of interface 'df_fifo_intf' [df_fifo_interface.sv:4]
WARNING: [VRFC 10-3609] overwriting previous definition of interface 'df_process_intf' [df_process_interface.sv:4]
WARNING: [VRFC 10-3609] overwriting previous definition of interface 'nodf_module_intf' [nodf_module_interface.sv:4]
INFO: [VRFC 10-311] analyzing module dataflow_monitor
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/override_llvm_flow_demo/proj/solution1/sim/verilog/csv_file_dump.sv" into library xil_defaultlib
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/override_llvm_flow_demo/proj/solution1/sim/verilog/nodf_module_interface.sv" into library xil_defaultlib
WARNING: [VRFC 10-3609] overwriting previous definition of interface 'nodf_module_intf' [/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/override_llvm_flow_demo/proj/solution1/sim/verilog/nodf_module_interface.sv:4]
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/override_llvm_flow_demo/proj/solution1/sim/verilog/df_process_monitor.sv" into library xil_defaultlib
WARNING: [VRFC 10-3609] overwriting previous definition of interface 'df_process_intf' [df_process_interface.sv:4]
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/override_llvm_flow_demo/proj/solution1/sim/verilog/df_fifo_monitor.sv" into library xil_defaultlib
WARNING: [VRFC 10-3609] overwriting previous definition of interface 'df_fifo_intf' [df_fifo_interface.sv:4]
Starting static elaboration
Pass Through NonSizing Optimizer
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package xil_defaultlib.$unit_dataflow_monitor_sv
Compiling module xil_defaultlib.example_a_m_axi_reg_slice(N=96)
Compiling module xil_defaultlib.example_a_m_axi_fifo(DATA_BITS=9...
Compiling module xil_defaultlib.example_a_m_axi_buffer(DATA_WIDT...
Compiling module xil_defaultlib.example_a_m_axi_fifo(DEPTH=5,DEP...
Compiling module xil_defaultlib.example_a_m_axi_fifo(DATA_BITS=2...
Compiling module xil_defaultlib.example_a_m_axi_fifo(DATA_BITS=2...
Compiling module xil_defaultlib.example_a_m_axi_write(NUM_WRITE_...
Compiling module xil_defaultlib.example_a_m_axi_buffer(DATA_WIDT...
Compiling module xil_defaultlib.example_a_m_axi_reg_slice(N=34)
Compiling module xil_defaultlib.example_a_m_axi_read(NUM_READ_OU...
Compiling module xil_defaultlib.example_a_m_axi_throttle(ADDR_WI...
Compiling module xil_defaultlib.example_a_m_axi(NUM_READ_OUTSTAN...
Compiling module xil_defaultlib.example_b_m_axi_reg_slice(N=96)
Compiling module xil_defaultlib.example_b_m_axi_fifo(DATA_BITS=9...
Compiling module xil_defaultlib.example_b_m_axi_buffer(DATA_WIDT...
Compiling module xil_defaultlib.example_b_m_axi_fifo(DEPTH=5,DEP...
Compiling module xil_defaultlib.example_b_m_axi_fifo(DATA_BITS=2...
Compiling module xil_defaultlib.example_b_m_axi_fifo(DATA_BITS=2...
Compiling module xil_defaultlib.example_b_m_axi_write(NUM_WRITE_...
Compiling module xil_defaultlib.example_b_m_axi_buffer(DATA_WIDT...
Compiling module xil_defaultlib.example_b_m_axi_reg_slice(N=34)
Compiling module xil_defaultlib.example_b_m_axi_read(NUM_READ_OU...
Compiling module xil_defaultlib.example_b_m_axi_throttle(ADDR_WI...
Compiling module xil_defaultlib.example_b_m_axi(NUM_READ_OUTSTAN...
Compiling module xil_defaultlib.example_add_6ns_6ns_6_1_1_Adder_...
Compiling module xil_defaultlib.example_add_6ns_6ns_6_1_1(ID=1,N...
Compiling module xil_defaultlib.example_add_32ns_32ns_32_2_1_Add...
Compiling module xil_defaultlib.example_add_32ns_32ns_32_2_1_Add...
Compiling module xil_defaultlib.example_add_32ns_32ns_32_2_1(ID=...
Compiling module xil_defaultlib.example
Compiling module xil_defaultlib.AESL_axi_master_a
Compiling module xil_defaultlib.AESL_axi_master_b
Compiling module xil_defaultlib.nodf_module_intf
Compiling module xil_defaultlib.dataflow_monitor_1
Compiling module xil_defaultlib.apatb_example_top
Compiling module work.glbl
Built simulation snapshot example
****** Webtalk v2020.2 (64-bit)
**** SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
**** IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020
** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
source /media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/override_llvm_flow_demo/proj/solution1/sim/verilog/xsim.dir/example/webtalk/xsim_webtalk.tcl -notrace
INFO: [Common 17-206] Exiting Webtalk at Tue Mar 9 20:33:12 2021...
****** xsim v2020.2 (64-bit)
**** SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
**** IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020
** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
source xsim.dir/example/xsim_script.tcl
# xsim {example} -autoloadwcfg -tclbatch {example.tcl}
Vivado Simulator 2020.2
Time resolution is 1 ps
source example.tcl
## run all
////////////////////////////////////////////////////////////////////////////////////
// Inter-Transaction Progress: Completed Transaction / Total Transaction
// Intra-Transaction Progress: Measured Latency / Latency Estimation * 100%
//
// RTL Simulation : "Inter-Transaction Progress" ["Intra-Transaction Progress"] @ "Simulation Time"
////////////////////////////////////////////////////////////////////////////////////
// RTL Simulation : 0 / 1 [0.00%] @ "109000"
// RTL Simulation : 1 / 1 [100.00%] @ "362000"
////////////////////////////////////////////////////////////////////////////////////
$finish called at time : 375750 ps : File "/media/masaaki/Ubuntu_Disk/Xilinx_github/HLS/vitis_hls_examples/override_llvm_flow_demo/proj/solution1/sim/verilog/example.autotb.v" Line 462
## quit
INFO: [Common 17-206] Exiting xsim at Tue Mar 9 20:33:33 2021...
INFO: [COSIM 212-316] Starting C post checking ...
Test passed.
INFO: [COSIM 212-1000] *** C/RTL co-simulation finished: PASS ***
INFO: [COSIM 212-211] II is measurable only when transaction number is greater than 1 in RTL simulation. Otherwise, they will be marked as all NA. If user wants to calculate them, please make sure there are at least 2 transactions in RTL simulation.
INFO: [HLS 200-111] Finished Command cosim_design CPU user time: 28.19 seconds. CPU system time: 2.01 seconds. Elapsed time: 45.23 seconds; current allocated memory: 212.210 MB.
INFO: [HLS 200-112] Total CPU user time: 57.29 seconds. Total CPU system time: 4.44 seconds. Total elapsed time: 101.39 seconds; peak allocated memory: 207.484 MB.
INFO: [Common 17-206] Exiting vitis_hls at Tue Mar 9 20:33:34 2021...
process_begin: CreateProcess(NULL, #echo "Copying 'xpwm.h' to '../../../include/xpwm.h'", ...) failed.
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