-- General configuration for OpenCV 3.4.9 =====================================
-- Version control: unknown
--
-- Extra modules:
-- Location (extra): /home/marsee/opencv_contrib/modules
-- Version control (extra): unknown
--
-- Platform:
-- Timestamp: 2021-12-29T11:50:57Z
-- Host: Linux 5.10.60.1-microsoft-standard-WSL2 x86_64
-- CMake: 3.10.2
-- CMake generator: Unix Makefiles
-- CMake build tool: /usr/bin/make
-- Configuration: RELEASE
--
-- CPU/HW features:
-- Baseline: SSE SSE2 SSE3
-- requested: SSE3
-- Dispatched code generation: SSE4_1 SSE4_2 FP16 AVX AVX2 AVX512_SKX
-- requested: SSE4_1 SSE4_2 AVX FP16 AVX2 AVX512_SKX
-- SSE4_1 (15 files): + SSSE3 SSE4_1
-- SSE4_2 (2 files): + SSSE3 SSE4_1 POPCNT SSE4_2
-- FP16 (1 files): + SSSE3 SSE4_1 POPCNT SSE4_2 FP16 AVX
-- AVX (6 files): + SSSE3 SSE4_1 POPCNT SSE4_2 AVX
-- AVX2 (28 files): + SSSE3 SSE4_1 POPCNT SSE4_2 FP16 FMA3 AVX AVX2
-- AVX512_SKX (6 files): + SSSE3 SSE4_1 POPCNT SSE4_2 FP16 FMA3 AVX AVX2 AVX_512F AVX512_COMMON AVX512_SKX
--
-- C/C++:
-- Built as dynamic libs?: YES
-- C++11: YES
-- C++ Compiler: /usr/bin/c++ (ver 7.5.0)
-- C++ flags (Release): -fsigned-char -ffast-math -W -Wall -Werror=return-type -Werror=non-virtual-dtor -Werror=address -Werror=sequence-point -Wformat -Werror=format-security -Wmissing-declarations -Wundef -Winit-self -Wpointer-arith -Wshadow -Wsign-promo -Wuninitialized -Winit-self -Wsuggest-override -Wno-delete-non-virtual-dtor -Wno-comment -Wimplicit-fallthrough=3 -Wno-strict-overflow -fdiagnostics-show-option -Wno-long-long -pthread -fomit-frame-pointer -ffunction-sections -fdata-sections -msse -msse2 -msse3 -fvisibility=hidden -fvisibility-inlines-hidden -O3 -DNDEBUG -DNDEBUG
-- C++ flags (Debug): -fsigned-char -ffast-math -W -Wall -Werror=return-type -Werror=non-virtual-dtor -Werror=address -Werror=sequence-point -Wformat -Werror=format-security -Wmissing-declarations -Wundef -Winit-self -Wpointer-arith -Wshadow -Wsign-promo -Wuninitialized -Winit-self -Wsuggest-override -Wno-delete-non-virtual-dtor -Wno-comment -Wimplicit-fallthrough=3 -Wno-strict-overflow -fdiagnostics-show-option -Wno-long-long -pthread -fomit-frame-pointer -ffunction-sections -fdata-sections -msse -msse2 -msse3 -fvisibility=hidden -fvisibility-inlines-hidden -g -O0 -DDEBUG -D_DEBUG
-- C Compiler: /usr/bin/cc
-- C flags (Release): -fsigned-char -ffast-math -W -Wall -Werror=return-type -Werror=non-virtual-dtor -Werror=address -Werror=sequence-point -Wformat -Werror=format-security -Wmissing-declarations -Wmissing-prototypes -Wstrict-prototypes -Wundef -Winit-self -Wpointer-arith -Wshadow -Wuninitialized -Winit-self -Wno-comment -Wimplicit-fallthrough=3 -Wno-strict-overflow -fdiagnostics-show-option -Wno-long-long -pthread -fomit-frame-pointer -ffunction-sections -fdata-sections -msse -msse2 -msse3 -fvisibility=hidden -O3 -DNDEBUG -DNDEBUG
-- C flags (Debug): -fsigned-char -ffast-math -W -Wall -Werror=return-type -Werror=non-virtual-dtor -Werror=address -Werror=sequence-point -Wformat -Werror=format-security -Wmissing-declarations -Wmissing-prototypes -Wstrict-prototypes -Wundef -Winit-self -Wpointer-arith -Wshadow -Wuninitialized -Winit-self -Wno-comment -Wimplicit-fallthrough=3 -Wno-strict-overflow -fdiagnostics-show-option -Wno-long-long -pthread -fomit-frame-pointer -ffunction-sections -fdata-sections -msse -msse2 -msse3 -fvisibility=hidden -g -O0 -DDEBUG -D_DEBUG
-- Linker flags (Release): -Wl,--gc-sections
-- Linker flags (Debug): -Wl,--gc-sections
-- ccache: YES
-- Precompiled headers: NO
-- Extra dependencies: dl m pthread rt
-- 3rdparty dependencies:
--
-- OpenCV modules:
-- To be built: aruco bgsegm bioinspired calib3d ccalib core datasets dnn dnn_objdetect dpm face features2d flann freetype fuzzy hfs highgui img_hash imgcodecs imgproc line_descriptor ml objdetect optflow phase_unwrapping photo plot python3 reg rgbd saliency shape stereo stitching structured_light superres surface_matching text tracking ts video videoio videostab xfeatures2d ximgproc xobjdetect xphoto
-- Disabled: world
-- Disabled by dependency: -
-- Unavailable: cnn_3dobj cudaarithm cudabgsegm cudacodec cudafeatures2d cudafilters cudaimgproc cudalegacy cudaobjdetect cudaoptflow cudastereo cudawarping cudev cvv hdf java js matlab ovis python2 sfm viz
-- Applications: tests perf_tests examples apps
-- Documentation: NO
-- Non-free algorithms: NO
--
-- GUI:
-- GTK+: YES (ver 3.22.30)
-- GThread : YES (ver 2.56.4)
-- GtkGlExt: NO
-- OpenGL support: NO
-- VTK support: NO
--
-- Media I/O:
-- ZLib: /usr/lib/x86_64-linux-gnu/libz.so (ver 1.2.11)
-- JPEG: /usr/lib/x86_64-linux-gnu/libjpeg.so (ver 80)
-- WEBP: /usr/lib/x86_64-linux-gnu/libwebp.so (ver encoder: 0x020e)
-- PNG: /usr/lib/x86_64-linux-gnu/libpng.so (ver 1.6.34)
-- TIFF: /usr/lib/x86_64-linux-gnu/libtiff.so (ver 42 / 4.0.9)
-- JPEG 2000: build (ver 1.900.1)
-- OpenEXR: build (ver 2.3.0)
-- HDR: YES
-- SUNRASTER: YES
-- PXM: YES
--
-- Video I/O:
-- DC1394: NO
-- FFMPEG: YES
-- avcodec: YES (ver 57.107.100)
-- avformat: YES (ver 57.83.100)
-- avutil: YES (ver 55.78.100)
-- swscale: YES (ver 4.8.100)
-- avresample: NO
-- GStreamer: YES
-- base: YES (ver 1.14.5)
-- video: YES (ver 1.14.5)
-- app: YES (ver 1.14.5)
-- riff: YES (ver 1.14.5)
-- pbutils: YES (ver 1.14.5)
-- libv4l/libv4l2: NO
-- v4l/v4l2: linux/videodev2.h
--
-- Parallel framework: pthreads
--
-- Trace: YES (with Intel ITT)
--
-- Other third-party libraries:
-- Intel IPP: 2019.0.0 Gold [2019.0.0]
-- at: /home/marsee/opencv/build/3rdparty/ippicv/ippicv_lnx/icv
-- Intel IPP IW: sources (2019.0.0)
-- at: /home/marsee/opencv/build/3rdparty/ippicv/ippicv_lnx/iw
-- Lapack: NO
-- Eigen: NO
-- Custom HAL: NO
-- Protobuf: build (3.5.1)
--
-- NVIDIA CUDA: NO
--
-- OpenCL: YES (no extra features)
-- Include path: /home/marsee/opencv/3rdparty/include/opencl/1.2
-- Link libraries: Dynamic load
--
-- Python 3:
-- Interpreter: /usr/bin/python3.6 (ver 3.6.9)
-- Libraries: /usr/lib/x86_64-linux-gnu/libpython3.6m.so (ver 3.6.9)
-- numpy: /usr/include/python3.6m/numpy (ver 1.13.3)
-- install path: lib/python3.6/dist-packages/cv2/python-3.6
--
-- Python (for build): /usr/bin/python2.7
--
-- Java:
-- ant: NO
-- JNI: NO
-- Java wrappers: NO
-- Java tests: NO
--
-- Install to: /usr/local
-- -----------------------------------------------------------------
--
-- Configuring done
-- Generating done
CMake Warning:
Manually-specified variables were not used by the project:
CUDA_ARCH_BIN
CUDA_ARCH_PTX
-- Build files have been written to: /home/marsee/opencv/build
// file_test2.c
// 2021/12/22 by marsee
// I wrote file_test2.c referring to xilffs_polled_example.c.
// Reference Links: https://github.com/Xilinx/embeddedsw/blob/master/lib/sw_services/xilffs/examples/xilffs_polled_example.c
// Measure the write time interval with XTime_GetTime()
#include "xparameters.h" /* SDK generated parameters */
#include "xsdps.h" /* SD device driver */
#include "ff.h"
#include "xil_cache.h"
#include "xplatform_info.h"
#include "string.h"
#include "stdio.h"
#include "xtime_l.h"
#define WAIT_MS 3.333 // 3.333 ms = 300 Hz
static FIL fil; /* File object */
static FATFS fatfs;
/*
* To test logical drive 0, FileName should be "0:/<File name>" or
* "<file_name>". For logical drive 1, FileName should be "1:/<file_name>"
*/
static char FileName[32] = "Test.txt";
static char *SD_File;
int main(void)
{
FRESULT Res;
UINT NumBytesRead;
UINT NumBytesWritten;
BYTE work[FF_MAX_SS];
XTime time;
double for_time[100];
double time_ms, time_ms_n;
/*
* To test logical drive 0, Path should be "0:/"
* For logical drive 1, Path should be "1:/"
*/
TCHAR *Path = "0:/";
u8 out_str[80] __attribute__ ((aligned(32)));
printf("SD write File System Test\n");
sprintf(out_str, "36000000,140000000,54004,0,fc55,151,feec8\n");
/*
* Register volume work area, initialize device
*/
Res = f_mount(&fatfs, Path, 0);
if (Res != FR_OK) {
return XST_FAILURE;
}
/*
* Path - Path to logical driver, 0 - FDISK format.
* 0 - Cluster size is automatically determined based on Vol size.
*/
Res = f_mkfs(Path, FM_FAT32, 0, work, sizeof work);
if (Res != FR_OK) {
return XST_FAILURE;
}
/*
* Open file with required permissions.
* Here - Creating new file with read/write permissions. .
* To open file with write permissions, file system should not
* be in Read Only mode.
*/
SD_File = (char *)FileName;
Res = f_open(&fil, SD_File, FA_CREATE_ALWAYS | FA_WRITE | FA_READ);
if (Res) {
return XST_FAILURE;
}
/*
* Pointer to beginning of file .
*/
Res = f_lseek(&fil, 0);
if (Res) {
return XST_FAILURE;
}
XTime_GetTime(&time);
time_ms = (double)((long long int)time)/333333.3435;
/*
* Write data to file.
*/
for (int i=0; i<100; i++){
int len_num = strlen(out_str);
Res = f_write(&fil, (const void*)out_str, len_num,
&NumBytesWritten);
do {
XTime_GetTime(&time);
time_ms_n = (double)((long long int)time)/333333.3435;
usleep(10); // 10us Wait
} while((time_ms_n - time_ms) < WAIT_MS);
time_ms = time_ms_n;
for_time[i] = time_ms;
if (Res) {
return XST_FAILURE;
}
}
for (int i=0; i<100; i++){
if(i == 0)
printf("%2d %lf\n", i, for_time[i]);
else
printf("%2d %lf, %lf\n", i, for_time[i], for_time[i]-for_time[i-1]);
}
/*
* Close file.
*/
Res = f_close(&fil);
if (Res) {
return XST_FAILURE;
}
printf("Done\n");
return 0;
}
SD write File System Test
0 3754.031451
1 3757.366112, 3.334662
2 3760.700624, 3.334512
3 3764.035142, 3.334518
4 3767.369630, 3.334488
5 3770.704151, 3.334521
6 3774.038639, 3.334488
7 3777.373151, 3.334512
8 3780.707639, 3.334488
9 3784.042160, 3.334521
10 3787.376647, 3.334488
11 3790.711159, 3.334512
12 3794.050537, 3.339378
13 3797.385565, 3.335028
14 3800.720050, 3.334485
15 3804.054568, 3.334518
16 3807.389059, 3.334491
17 3810.723595, 3.334536
18 3814.058086, 3.334491
19 3817.392607, 3.334521
20 3820.727091, 3.334485
21 3824.061612, 3.334521
22 3827.396103, 3.334491
23 3830.730624, 3.334521
24 3834.070485, 3.339861
25 3837.405012, 3.334527
26 3840.739503, 3.334491
27 3844.074024, 3.334521
28 3847.408512, 3.334488
29 3850.743042, 3.334530
30 3854.077529, 3.334488
31 3857.412047, 3.334518
32 3860.746538, 3.334491
33 3864.081071, 3.334533
34 3867.415556, 3.334485
35 3870.750074, 3.334518
36 3874.090523, 3.340449
37 3877.425050, 3.334527
38 3880.759541, 3.334491
39 3884.094062, 3.334521
40 3887.428546, 3.334485
41 3890.763067, 3.334521
42 3894.097558, 3.334491
43 3897.432079, 3.334521
44 3900.766567, 3.334488
45 3904.101100, 3.334533
46 3907.435585, 3.334485
47 3910.770103, 3.334518
48 3914.113009, 3.342906
49 3917.447539, 3.334530
50 3920.782023, 3.334485
51 3924.116538, 3.334515
52 3927.451026, 3.334488
53 3930.785556, 3.334530
54 3934.120044, 3.334488
55 3937.454565, 3.334521
56 3940.789050, 3.334485
57 3944.123571, 3.334521
58 3947.458062, 3.334491
59 3950.792583, 3.334521
60 3954.128240, 3.335658
61 3957.462794, 3.334554
62 3960.797309, 3.334515
63 3964.131821, 3.334512
64 3967.466312, 3.334491
65 3970.800848, 3.334536
66 3974.135339, 3.334491
67 3977.469857, 3.334518
68 3980.804348, 3.334491
69 3984.138877, 3.334530
70 3987.473365, 3.334488
71 3990.807886, 3.334521
72 3994.142374, 3.334488
73 3997.481614, 3.339240
74 4000.816117, 3.334503
75 4004.150638, 3.334521
76 4007.485126, 3.334488
77 4010.819656, 3.334530
78 4014.154144, 3.334488
79 4017.488661, 3.334518
80 4020.823152, 3.334491
81 4024.157685, 3.334533
82 4027.492170, 3.334485
83 4030.826688, 3.334518
84 4034.161179, 3.334491
85 4037.497716, 3.336537
86 4040.832201, 3.334485
87 4044.166713, 3.334512
88 4047.501204, 3.334491
89 4050.835730, 3.334527
90 4054.170221, 3.334491
91 4057.504742, 3.334521
92 4060.839230, 3.334488
93 4064.173760, 3.334530
94 4067.508248, 3.334488
95 4070.842766, 3.334518
96 4074.177257, 3.334491
97 4077.517997, 3.340740
98 4080.852500, 3.334503
99 4084.187014, 3.334515
Done
で書き込み時間間隔を測定するソフトウェアとなっている。XTime_GetTime(&time);
// file_test.c
// 2021/12/22 by marsee
// I wrote file_test2.c referring to xilffs_polled_example.c.
//@Reference Links: https://github.com/Xilinx/embeddedsw/blob/master/lib/sw_services/xilffs/examples/xilffs_polled_example.c
// Measure the write time interval with XTime_GetTime()
#include "xparameters.h" /* SDK generated parameters */
#include "xsdps.h" /* SD device driver */
#include "ff.h"
#include "xil_cache.h"
#include "xplatform_info.h"
#include "string.h"
#include "stdio.h"
#include "xtime_l.h"
static FIL fil; /* File object */
static FATFS fatfs;
/*
* To test logical drive 0, FileName should be "0:/<File name>" or
* "<file_name>". For logical drive 1, FileName should be "1:/<file_name>"
*/
static char FileName[32] = "Test.txt";
static char *SD_File;
int main(void)
{
FRESULT Res;
UINT NumBytesRead;
UINT NumBytesWritten;
BYTE work[FF_MAX_SS];
XTime time;
double for_time[100];
/*
* To test logical drive 0, Path should be "0:/"
* For logical drive 1, Path should be "1:/"
*/
TCHAR *Path = "0:/";
u8 out_str[80] __attribute__ ((aligned(32)));
printf("SD write File System Test\n");
sprintf(out_str, "36000000,140000000,54004,0,fc55,151,feec8\n");
/*
* Register volume work area, initialize device
*/
Res = f_mount(&fatfs, Path, 0);
if (Res != FR_OK) {
return XST_FAILURE;
}
/*
* Path - Path to logical driver, 0 - FDISK format.
* 0 - Cluster size is automatically determined based on Vol size.
*/
Res = f_mkfs(Path, FM_FAT32, 0, work, sizeof work);
if (Res != FR_OK) {
return XST_FAILURE;
}
/*
* Open file with required permissions.
* Here - Creating new file with read/write permissions. .
* To open file with write permissions, file system should not
* be in Read Only mode.
*/
SD_File = (char *)FileName;
Res = f_open(&fil, SD_File, FA_CREATE_ALWAYS | FA_WRITE | FA_READ);
if (Res) {
return XST_FAILURE;
}
/*
* Pointer to beginning of file .
*/
Res = f_lseek(&fil, 0);
if (Res) {
return XST_FAILURE;
}
/*
* Write data to file.
*/
for (int i=0; i<100; i++){
int len_num = strlen(out_str);
Res = f_write(&fil, (const void*)out_str, len_num,
&NumBytesWritten);
XTime_GetTime(&time);
for_time[i] = (double)((long long int)time)/333333.3435; // ms
if (Res) {
return XST_FAILURE;
}
}
for (int i=0; i<100; i++){
if(i == 0)
printf("%2d %lf\n", i, for_time[i]);
else
printf("%2d %lf, %lf\n", i, for_time[i], for_time[i]-for_time[i-1]);
}
/*
* Close file.
*/
Res = f_close(&fil);
if (Res) {
return XST_FAILURE;
}
printf("Done\n");
return 0;
}
SD write File System Test
0 3045.713658
1 3045.714837, 0.001179
2 3045.715389, 0.000552
3 3045.715980, 0.000591
4 3045.716532, 0.000552
5 3045.717132, 0.000600
6 3045.717684, 0.000552
7 3045.718275, 0.000591
8 3045.718827, 0.000552
9 3045.719427, 0.000600
10 3045.719979, 0.000552
11 3045.720570, 0.000591
12 3046.690773, 0.970203
13 3046.691418, 0.000645
14 3046.692024, 0.000606
15 3046.692633, 0.000609
16 3046.693227, 0.000594
17 3046.693836, 0.000609
18 3046.694424, 0.000588
19 3046.695027, 0.000603
20 3046.695621, 0.000594
21 3046.696230, 0.000609
22 3046.696818, 0.000588
23 3046.697421, 0.000603
24 3048.589899, 1.892478
25 3048.590511, 0.000612
26 3048.591084, 0.000573
27 3048.591669, 0.000585
28 3048.592251, 0.000582
29 3048.592848, 0.000597
30 3048.593430, 0.000582
31 3048.594018, 0.000588
32 3048.594600, 0.000582
33 3048.595197, 0.000597
34 3048.595779, 0.000582
35 3048.596367, 0.000588
36 3049.652643, 1.056276
37 3049.653270, 0.000627
38 3049.653858, 0.000588
39 3049.654470, 0.000612
40 3049.655064, 0.000594
41 3049.655673, 0.000609
42 3049.656261, 0.000588
43 3049.656864, 0.000603
44 3049.657458, 0.000594
45 3049.658067, 0.000609
46 3049.658655, 0.000588
47 3049.659258, 0.000603
48 3051.551673, 1.892415
49 3051.552291, 0.000618
50 3051.552873, 0.000582
51 3051.553461, 0.000588
52 3051.554043, 0.000582
53 3051.554640, 0.000597
54 3051.555222, 0.000582
55 3051.555810, 0.000588
56 3051.556392, 0.000582
57 3051.556989, 0.000597
58 3051.557571, 0.000582
59 3051.558159, 0.000588
60 3052.645830, 1.087671
61 3052.646502, 0.000672
62 3052.647084, 0.000582
63 3052.647663, 0.000579
64 3052.648227, 0.000564
65 3052.648806, 0.000579
66 3052.649370, 0.000564
67 3052.649949, 0.000579
68 3052.650513, 0.000564
69 3052.651092, 0.000579
70 3052.651656, 0.000564
71 3052.652235, 0.000579
72 3052.652799, 0.000564
73 3054.500076, 1.847277
74 3054.500667, 0.000591
75 3054.501258, 0.000591
76 3054.501840, 0.000582
77 3054.502437, 0.000597
78 3054.503019, 0.000582
79 3054.503607, 0.000588
80 3054.504189, 0.000582
81 3054.504786, 0.000597
82 3054.505368, 0.000582
83 3054.505956, 0.000588
84 3054.506538, 0.000582
85 3055.595505, 1.088967
86 3055.596090, 0.000585
87 3055.596693, 0.000603
88 3055.597287, 0.000594
89 3055.597899, 0.000612
90 3055.598493, 0.000594
91 3055.599096, 0.000603
92 3055.599690, 0.000594
93 3055.600299, 0.000609
94 3055.600887, 0.000588
95 3055.601490, 0.000603
96 3055.602084, 0.000594
97 3057.558540, 1.956456
98 3057.559128, 0.000588
99 3057.559719, 0.000591
Done
set_property IOSTANDARD LVCMOS33 [get_ports {ld0[0]}]
set_property PACKAGE_PIN M14 [get_ports {ld0[0]}]
// ----------------------------------------------------------------------------
// Smart High-Level Synthesis Tool Version 2021.2
// Copyright (c) 2015-2021 Microchip Technology Inc. All Rights Reserved.
// For support, please contact: smarthls@microchip.com
// Date: Sat Dec 25 04:12:11 2021
// ----------------------------------------------------------------------------
SmartHLS Summary Report for Project: axi_initiator.
Table of Contents
1. RTL Interface
2. Scheduling Result
3. Pipeline Result
4. Memory Usage
5. Accelerator Information
6. Resource Binding with Adaptive Latency
====== 1. RTL Interface ======
+-------------------------------------------------------------------------------------------+
| RTL Interface Generated by SmartHLS |
+-----------+----------------+------------------------+------------------+------------------+
| C++ Name | Interface Type | Signal Name | Signal Bit-width | Signal Direction |
+-----------+----------------+------------------------+------------------+------------------+
| | Control | clk | 1 | input |
| | | finish | 1 | output |
| | | ready | 1 | output |
| | | reset | 1 | input |
| | | start | 1 | input |
+-----------+----------------+------------------------+------------------+------------------+
| initiator | AXI Master | initiator_ar_addr | 32 | output |
| | | initiator_ar_burst | 2 | output |
| | | initiator_ar_len | 8 | output |
| | | initiator_ar_ready | 1 | input |
| | | initiator_ar_size | 3 | output |
| | | initiator_ar_valid | 1 | output |
| | | initiator_aw_addr | 32 | output |
| | | initiator_aw_burst | 2 | output |
| | | initiator_aw_len | 8 | output |
| | | initiator_aw_ready | 1 | input |
| | | initiator_aw_size | 3 | output |
| | | initiator_aw_valid | 1 | output |
| | | initiator_b_resp | 2 | input |
| | | initiator_b_resp_ready | 1 | output |
| | | initiator_b_resp_valid | 1 | input |
| | | initiator_r_data | 64 | input |
| | | initiator_r_last | 1 | input |
| | | initiator_r_ready | 1 | output |
| | | initiator_r_resp | 2 | input |
| | | initiator_r_valid | 1 | input |
| | | initiator_w_data | 64 | output |
| | | initiator_w_last | 1 | output |
| | | initiator_w_ready | 1 | input |
| | | initiator_w_strb | 8 | output |
| | | initiator_w_valid | 1 | output |
+-----------+----------------+------------------------+------------------+------------------+
The Verilog top-level module ports that are not listed in the above table are unused. Please tie the unused input ports to 0.
====== 2. Scheduling Result ======
Please use SmartHLS's schedule viewer to examine the schedule.
Basic Block Latencies:
+-----------------------------------------------------+
| Function: simple_initiator (non-pipelined function) |
+---------------------------+-------------------------+
| Basic Block | Cycle Latency |
+---------------------------+-------------------------+
| %for.body.lr.ph | 1 |
| %for.body | 2 |
| %for.end | 1 |
+---------------------------+-------------------------+
====== 3. Pipeline Result ======
+---------------------------------+------------------+-------------+------------------------------+---------------------+-----------------+-----------------+---------+
| Label | Function | Basic Block | Location in Source Code | Initiation Interval | Pipeline Length | Iteration Count | Latency |
+---------------------------------+------------------+-------------+------------------------------+---------------------+-----------------+-----------------+---------+
| for_loop_axi_initiator_cpp_13_5 | simple_initiator | %for.body | line 13 of axi_initiator.cpp | 1 | 2 | 256 | 257 |
+---------------------------------+------------------+-------------+------------------------------+---------------------+-----------------+-----------------+---------+
====== 4. Memory Usage ======
+----------------+
| Local Memories |
+----------------+
| None |
+----------------+
+-------------------------+
| Local Constant Memories |
+-------------------------+
| None |
+-------------------------+
+-----------------------+
| Shared Local Memories |
+-----------------------+
| None |
+-----------------------+
+------------------+
| Aliased Memories |
+------------------+
| None |
+------------------+
+-----------------------------------------------------------------------------------------------+
| I/O Memories |
+--------------------+-----------------------+---------------+-------------+------------+-------+
| Name | Accessing Function(s) | Type | Size [Bits] | Data Width | Depth |
+--------------------+-----------------------+---------------+-------------+------------+-------+
| initiator_ar_addr | simple_initiator | FIFO (LUTRAM) | 0 | 32 | 0 |
| initiator_ar_burst | simple_initiator | FIFO (LUTRAM) | 0 | 2 | 0 |
| initiator_ar_size | simple_initiator | FIFO (LUTRAM) | 0 | 3 | 0 |
| initiator_ar_len | simple_initiator | FIFO (LUTRAM) | 0 | 8 | 0 |
| initiator_r_data | simple_initiator | FIFO (LUTRAM) | 0 | 64 | 0 |
| initiator_r_resp | simple_initiator | FIFO (LUTRAM) | 0 | 2 | 0 |
| initiator_r_last | simple_initiator | FIFO (LUTRAM) | 0 | 1 | 0 |
| initiator_aw_addr | simple_initiator | FIFO (LUTRAM) | 0 | 32 | 0 |
| initiator_aw_burst | simple_initiator | FIFO (LUTRAM) | 0 | 2 | 0 |
| initiator_aw_size | simple_initiator | FIFO (LUTRAM) | 0 | 3 | 0 |
| initiator_aw_len | simple_initiator | FIFO (LUTRAM) | 0 | 8 | 0 |
| initiator_w_data | simple_initiator | FIFO (LUTRAM) | 0 | 64 | 0 |
| initiator_w_strb | simple_initiator | FIFO (LUTRAM) | 0 | 8 | 0 |
| initiator_w_last | simple_initiator | FIFO (LUTRAM) | 0 | 1 | 0 |
| initiator_b_resp | simple_initiator | FIFO (LUTRAM) | 0 | 2 | 0 |
+--------------------+-----------------------+---------------+-------------+------------+-------+
====== 5. Accelerator Information ======
No accelerator function is generated.
====== 6. Resource Binding with Adaptive Latency ======
Binding to resource with adaptive latency is disabled.
You can enable this feature by setting config parameter 'ADAPTIVE_LATENCY_BINDING' to 1.
==================================================================
===== Summary Report for RTL Simulation and FPGA Synthesis =====
==================================================================
Project name: axi_initiator
FPGA Vendor: MICROSEMI
Device Family: PolarFire
Device: MPF300TS-1FCG1152I
Table of Contents
1. Simulation Cycle Latency
2. Timing Result
3. Resource Usage
====== 1. Simulation Cycle Latency ======
Number of calls: 1
Cycle latency: 261
SW/HW co-simulation: PASS
====== 2. Timing Result ======
+--------------+---------------+-------------+-------------+----------+-------------+
| Clock Domain | Target Period | Target Fmax | Worst Slack | Period | Fmax |
+--------------+---------------+-------------+-------------+----------+-------------+
| clk | 10.000 ns | 100.000 MHz | 7.647 ns | 2.353 ns | 424.989 MHz |
+--------------+---------------+-------------+-------------+----------+-------------+
The reported Fmax is for the HLS core in isolation (from Libero's post-place-and-route timing analysis).
When the HLS core is integrated into a larger system, the system Fmax may be lower depending on the critical path of the system.
====== 3. Resource Usage ======
+--------------------------+---------------+--------+------------+
| Resource Type | Used | Total | Percentage |
+--------------------------+---------------+--------+------------+
| Fabric + Interface 4LUT* | 428 + 0 = 428 | 299544 | 0.14 |
| Fabric + Interface DFF* | 206 + 0 = 206 | 299544 | 0.07 |
| I/O Register | 0 | 1536 | 0.00 |
| User I/O | 0 | 512 | 0.00 |
| uSRAM | 0 | 2772 | 0.00 |
| LSRAM | 0 | 952 | 0.00 |
| Math | 0 | 924 | 0.00 |
+--------------------------+---------------+--------+------------+
* Interface 4LUTs and DFFs are occupied due to the uses of LSRAM, Math, and uSRAM.
Number of interface 4LUTs/DFFs = (36 * #.LSRAM) + (36 * #.Math) + (12 * #.uSRAM) = (36 * 0) + (36 * 0) + (12 * 0) = 0.
#include <hls/axi_interface.hpp>
１． AxiInterface クラスのインスタンスを作成し、テンプレートパラメータを使用してアドレス幅、データ幅、およびwstrb幅を指定します。
2. トップレベル関数を参照して、作成したインスタンスを渡します。例えば、
void MyTop(AxiInterface, /* DATA: */ ap_uint<64>, /* WSTRB: */ ap_uint<8>> &master);
3. ヘッダーで定義されているユーティリティ関数（API）を使用して、AXIマスターインターフェイスを制御します。
// Request to read data in burst.
axi_m_read_req<ap_uint<32>, ap_uint<64>, ap_uint<8>>(initiator, r_addr, AXIM_MAX_BURST_LEN);
// Request to write data in burst.
axi_m_write_req<ap_uint<32>, ap_uint<64>, ap_uint<8>>(initiator, w_addr, AXIM_MAX_BURST_LEN);
// Write back the data we read + 1.
ap_uint<64> data = axi_m_read_data<ap_uint<32>, ap_uint<64>>(initiator);
axi_m_write_data<ap_uint<32>, ap_uint<64>, ap_uint<8>>(initiator, ap_uint<64>(data + 1), ap_uint<8>(0xFF), is_last);
// After the last write, read the response code.
ap_uint<2> bresp = axi_m_write_resp(initiator);
AXI4スレーブインターフェイスと同じように、このAXI4マスターインターフェイスライブラリは、バーストの追加サポートを備えたAXI4-liteプロトコルのみをサポートします。
SW / HW協調シミュレーションはAXIマスターでサポートされていますが、カーネルが呼び出される前に、ソフトウェアでAXIマスターに対するAXIスレーブの応答をモデル化する必要があります。
sum_result = 101010366
xor_result = fefefeea
or_result = ffffffff
PASS
// ----------------------------------------------------------------------------
// Smart High-Level Synthesis Tool Version 2021.2
// Copyright (c) 2015-2021 Microchip Technology Inc. All Rights Reserved.
// For support, please contact: smarthls@microchip.com
// Date: Wed Dec 22 20:32:01 2021
// ----------------------------------------------------------------------------
SmartHLS Summary Report for Project: axi_target.
Table of Contents
1. RTL Interface
2. Scheduling Result
3. Pipeline Result
4. Memory Usage
5. Accelerator Information
6. Resource Binding with Adaptive Latency
====== 1. RTL Interface ======
+-------------------------------------------------------------------------------------------+
| RTL Interface Generated by SmartHLS |
+---------------+----------------+--------------------+------------------+------------------+
| C++ Name | Interface Type | Signal Name | Signal Bit-width | Signal Direction |
+---------------+----------------+--------------------+------------------+------------------+
| | Control | clk | 1 | input |
| | | finish | 1 | output |
| | | ready | 1 | output |
| | | reset | 1 | input |
| | | start | 1 | input |
+---------------+----------------+--------------------+------------------+------------------+
| target_memory | AXI Slave | axi_s_ar_addr | 32 | input |
| | | axi_s_ar_burst | 2 | input |
| | | axi_s_ar_len | 8 | input |
| | | axi_s_ar_ready | 1 | output |
| | | axi_s_ar_size | 3 | input |
| | | axi_s_ar_valid | 1 | input |
| | | axi_s_aw_addr | 32 | input |
| | | axi_s_aw_burst | 2 | input |
| | | axi_s_aw_len | 8 | input |
| | | axi_s_aw_ready | 1 | output |
| | | axi_s_aw_size | 3 | input |
| | | axi_s_aw_valid | 1 | input |
| | | axi_s_b_resp | 2 | output |
| | | axi_s_b_resp_ready | 1 | input |
| | | axi_s_b_resp_valid | 1 | output |
| | | axi_s_r_data | 64 | output |
| | | axi_s_r_last | 1 | output |
| | | axi_s_r_ready | 1 | input |
| | | axi_s_r_resp | 2 | output |
| | | axi_s_r_valid | 1 | output |
| | | axi_s_w_data | 64 | input |
| | | axi_s_w_last | 1 | input |
| | | axi_s_w_ready | 1 | output |
| | | axi_s_w_strb | 8 | input |
| | | axi_s_w_valid | 1 | input |
+---------------+----------------+--------------------+------------------+------------------+
The Verilog top-level module ports that are not listed in the above table are unused. Please tie the unused input ports to 0.
====== 2. Scheduling Result ======
Please use SmartHLS's schedule viewer to examine the schedule.
Basic Block Latencies:
+------------------------------------------------+
| Function: calc_kernel (non-pipelined function) |
+-----------------------+------------------------+
| Basic Block | Cycle Latency |
+-----------------------+------------------------+
| %entry | 7 |
+-----------------------+------------------------+
+-----------------------------------------------------+
| Function: calc_kernel_orig (non-pipelined function) |
+-------------------------+---------------------------+
| Basic Block | Cycle Latency |
+-------------------------+---------------------------+
| %entry | 5 |
+-------------------------+---------------------------+
+----------------------------------------------------+
| Function: target_memory_write (pipelined function) |
+--------------------------+-------------------------+
| Basic Block | Cycle Latency |
+--------------------------+-------------------------+
| %init.check.i | 3 |
+--------------------------+-------------------------+
+---------------------------------------------------+
| Function: target_memory_read (pipelined function) |
+-------------------------+-------------------------+
| Basic Block | Cycle Latency |
+-------------------------+-------------------------+
| %init.check.i | 5 |
+-------------------------+-------------------------+
====== 3. Pipeline Result ======
+---------------------+---------------------+---------------+--------------------------------+---------------------+-----------------+-----------------+---------+
| Label | Function | Basic Block | Location in Source Code | Initiation Interval | Pipeline Length | Iteration Count | Latency |
+---------------------+---------------------+---------------+--------------------------------+---------------------+-----------------+-----------------+---------+
| target_memory_write | target_memory_write | %init.check.i | line 115 of axi_slave.mmap.tmp | 1 | 3 | n/a | n/a |
| target_memory_read | target_memory_read | %init.check.i | line 119 of axi_slave.mmap.tmp | 1 | 5 | n/a | n/a |
+---------------------+---------------------+---------------+--------------------------------+---------------------+-----------------+-----------------+---------+
====== 4. Memory Usage ======
+--------------------------------------------------------------------------------------------------------------------------------------------+
| Local Memories |
+---------------------------------------------------------+-----------------------+-----------------------+-------------+------------+-------+
| Name | Accessing Function(s) | Type | Size [Bits] | Data Width | Depth |
+---------------------------------------------------------+-----------------------+-----------------------+-------------+------------+-------+
| axi_s_read_state | target_memory_read | Register | 1 | 1 | 1 |
| axi_s_read_word_addr | target_memory_read | Register | 32 | 32 | 1 |
| init_flag_ZGVZ10axi_s_readIN3hls7ap_uintILj32EEENS | target_memory_read | Register (Write-Only) | 1 | 1 | 1 |
| init_flag_ZGVZ10axi_s_readIN3hls7ap_uintILj32EEENS_var0 | target_memory_read | Register (Write-Only) | 1 | 1 | 1 |
| init_flag_ZGVZ11axi_s_writeIN3hls7ap_uintILj32EEEN | target_memory_write | Register (Write-Only) | 1 | 1 | 1 |
| init_flag_ZGVZ10axi_s_readIN3hls7ap_uintILj32EEENS_var1 | target_memory_read | Register (Write-Only) | 1 | 1 | 1 |
| axi_s_read_burst_len_minus1 | target_memory_read | Register | 8 | 8 | 1 |
| axi_s_read_count | target_memory_read | Register | 8 | 8 | 1 |
| axi_s_write_state | target_memory_write | Register | 1 | 1 | 1 |
| axi_s_write_word_addr | target_memory_write | Register | 32 | 32 | 1 |
| axi_s_write_count | target_memory_write | Register | 8 | 8 | 1 |
| init_flag_ZGVZ11axi_s_writeIN3hls7ap_uintILj32EEEN_var0 | target_memory_write | Register (Write-Only) | 1 | 1 | 1 |
+---------------------------------------------------------+-----------------------+-----------------------+-------------+------------+-------+
+-------------------------+
| Local Constant Memories |
+-------------------------+
| None |
+-------------------------+
+------------------------------------------------------------------------------------------------------------------------------------+
| Shared Local Memories |
+--------------------------+-----------------------------------------------------------+----------+-------------+------------+-------+
| Name | Accessing Function(s) | Type | Size [Bits] | Data Width | Depth |
+--------------------------+-----------------------------------------------------------+----------+-------------+------------+-------+
| target_memory_arr_a0 | calc_kernel_orig, target_memory_read, target_memory_write | Register | 8 | 8 | 1 |
| target_memory_arr_a1 | calc_kernel_orig, target_memory_read, target_memory_write | Register | 8 | 8 | 1 |
| target_memory_arr_a2 | calc_kernel_orig, target_memory_read, target_memory_write | Register | 8 | 8 | 1 |
| target_memory_arr_a3 | calc_kernel_orig, target_memory_read, target_memory_write | Register | 8 | 8 | 1 |
| target_memory_arr_a4 | calc_kernel_orig, target_memory_read, target_memory_write | Register | 8 | 8 | 1 |
| target_memory_arr_a5 | calc_kernel_orig, target_memory_read, target_memory_write | Register | 8 | 8 | 1 |
| target_memory_arr_a6 | calc_kernel_orig, target_memory_read, target_memory_write | Register | 8 | 8 | 1 |
| target_memory_arr_a7 | calc_kernel_orig, target_memory_read, target_memory_write | Register | 8 | 8 | 1 |
| target_memory_a | calc_kernel_orig, target_memory_read, target_memory_write | Register | 32 | 32 | 1 |
| target_memory_b | calc_kernel_orig, target_memory_read, target_memory_write | Register | 32 | 32 | 1 |
| target_memory_sum_result | calc_kernel_orig, target_memory_read, target_memory_write | Register | 64 | 64 | 1 |
| target_memory_xor_result | calc_kernel_orig, target_memory_read, target_memory_write | Register | 32 | 32 | 1 |
| target_memory_or_result | calc_kernel_orig, target_memory_read, target_memory_write | Register | 32 | 32 | 1 |
| target_memory_ctrl | target_memory_read, target_memory_write | Register | 1 | 1 | 1 |
+--------------------------+-----------------------------------------------------------+----------+-------------+------------+-------+
+------------------+
| Aliased Memories |
+------------------+
| None |
+------------------+
+-------------------------------------------------------------------------------------------+
| I/O Memories |
+----------------+-----------------------+---------------+-------------+------------+-------+
| Name | Accessing Function(s) | Type | Size [Bits] | Data Width | Depth |
+----------------+-----------------------+---------------+-------------+------------+-------+
| axi_s_ar_addr | target_memory_read | FIFO (LUTRAM) | 0 | 32 | 0 |
| axi_s_ar_burst | target_memory_read | FIFO (LUTRAM) | 0 | 2 | 0 |
| axi_s_ar_size | target_memory_read | FIFO (LUTRAM) | 0 | 3 | 0 |
| axi_s_ar_len | target_memory_read | FIFO (LUTRAM) | 0 | 8 | 0 |
| axi_s_r_data | target_memory_read | FIFO (LUTRAM) | 0 | 64 | 0 |
| axi_s_r_resp | target_memory_read | FIFO (LUTRAM) | 0 | 2 | 0 |
| axi_s_r_last | target_memory_read | FIFO (LUTRAM) | 0 | 1 | 0 |
| axi_s_aw_addr | target_memory_write | FIFO (LUTRAM) | 0 | 32 | 0 |
| axi_s_aw_burst | target_memory_write | FIFO (LUTRAM) | 0 | 2 | 0 |
| axi_s_aw_size | target_memory_write | FIFO (LUTRAM) | 0 | 3 | 0 |
| axi_s_aw_len | target_memory_write | FIFO (LUTRAM) | 0 | 8 | 0 |
| axi_s_w_data | target_memory_write | FIFO (LUTRAM) | 0 | 64 | 0 |
| axi_s_w_strb | target_memory_write | FIFO (LUTRAM) | 0 | 8 | 0 |
| axi_s_w_last | target_memory_write | FIFO (LUTRAM) | 0 | 1 | 0 |
| axi_s_b_resp | target_memory_write | FIFO (LUTRAM) | 0 | 2 | 0 |
+----------------+-----------------------+---------------+-------------+------------+-------+
====== 5. Accelerator Information ======
No accelerator function is generated.
====== 6. Resource Binding with Adaptive Latency ======
Binding to resource with adaptive latency is disabled.
You can enable this feature by setting config parameter 'ADAPTIVE_LATENCY_BINDING' to 1.
==================================================================
===== Summary Report for RTL Simulation and FPGA Synthesis =====
==================================================================
Project name: axi_target
FPGA Vendor: MICROSEMI
Device Family: PolarFire
Device: MPF300TS-1FCG1152I
Table of Contents
1. Simulation Cycle Latency
2. Timing Result
3. Resource Usage
====== 1. Simulation Cycle Latency ======
Number of calls: 1
Cycle latency: 17
SW/HW co-simulation: PASS
====== 2. Timing Result ======
+--------------+---------------+-------------+-------------+----------+-------------+
| Clock Domain | Target Period | Target Fmax | Worst Slack | Period | Fmax |
+--------------+---------------+-------------+-------------+----------+-------------+
| clk | 10.000 ns | 100.000 MHz | 7.625 ns | 2.375 ns | 421.053 MHz |
+--------------+---------------+-------------+-------------+----------+-------------+
The reported Fmax is for the HLS core in isolation (from Libero's post-place-and-route timing analysis).
When the HLS core is integrated into a larger system, the system Fmax may be lower depending on the critical path of the system.
====== 3. Resource Usage ======
+--------------------------+-----------------+--------+------------+
| Resource Type | Used | Total | Percentage |
+--------------------------+-----------------+--------+------------+
| Fabric + Interface 4LUT* | 985 + 0 = 985 | 299544 | 0.33 |
| Fabric + Interface DFF* | 1230 + 0 = 1230 | 299544 | 0.41 |
| I/O Register | 0 | 1536 | 0.00 |
| User I/O | 0 | 512 | 0.00 |
| uSRAM | 0 | 2772 | 0.00 |
| LSRAM | 0 | 952 | 0.00 |
| Math | 0 | 924 | 0.00 |
+--------------------------+-----------------+--------+------------+
* Interface 4LUTs and DFFs are occupied due to the uses of LSRAM, Math, and uSRAM.
Number of interface 4LUTs/DFFs = (36 * #.LSRAM) + (36 * #.Math) + (12 * #.uSRAM) = (36 * 0) + (36 * 0) + (12 * 0) = 0.
重要：AXI4スレーブにはいくつかの制限があります。
・SmartHLSモジュールは最大で1つのAXI4スレーブインターフェイスを持つことができ、AXI4スレーブインターフェイスタイプは、構造体データタイプのグローバル変数に対してのみ指定できます。
・複数のデータをAXI4スレーブインターフェイスの背後に配置する必要がある場合は、すべてのデータを含む新しい構造体タイプを定義してから、構造体タイプでグローバル変数をインスタンス化し、グローバル変数に上記のプラグマを指定できます。
・AXI4スレーブインターフェイスは常に32ビットアドレスと64ビットデータ幅を使用します。
・AXI4スレーブインターフェイスは、インクリメンタルバーストの追加サポートを備えたAXI4-liteプロトコルのみをサポートします。
・AxBURSTおよびAxSIZE入力信号は、スレーブロジックによって無視されます。
・AxBURSTおよびAxSIZE信号の実際の入力値に関係なく、AXI4スレーブは常にインクリメンタルバーストタイプ（AxBURST == 1）を使用し、転送あたりのサイズは8バイト（AxSIZE == 3）です。
・バイトイネーブル書き込み（WSTRBポート経由）は、構造体の要素に揃える必要があります。
・共通の構造体要素（の異なるバイト）に対応するWSTRBビットの場合、これらのWSTRBビットはすべて1またはすべて0である必要があります。
・たとえば、2つの「int」型整数（それぞれ4バイト、1つの64ビットAXIワードとして一緒にパック）にマップするワードアドレスに書き込む場合、WSTRBポートの上位4ビットはすべて1または0である必要があります。 、および同じことがWSTRBポートの下位4ビットにも当てはまります。つまり、どちらの 'int'型整数の部分バイトも更新できませんが、2つの 'int'型整数のいずれかのすべてのバイトを更新することはできます。
・SW / HW協調シミュレーションは、最上位機能がパイプライン化されていない場合にのみサポートされます。
・AXI4スレーブインターフェイスを使用する場合、最上位関数はvoid戻り型を使用する必要があります。
のプラグマを付けるようだ。#pragma HLS interface variable(target_memory) type(axi_slave) （注： concurrent_access(true|false) というオプションもあるようだ）
struct TargetLayout target_memory;
#ifndef __AXI_TARGET_H__
#define __AXI_TARGET_H__
#include <cstdint>
struct TargetLayout {
uint8_t arr[8];
uint32_t a;
uint32_t b;
uint64_t sum_result;
uint32_t xor_result;
uint32_t or_result;
};
#endif // __AXI_TARGET_H__
// ----------------------------------------------------------------------------
// Smart High-Level Synthesis Tool Version 2021.2
// Copyright (c) 2015-2021 Microchip Technology Inc. All Rights Reserved.
// For support, please contact: smarthls@microchip.com
// Date: Sun Dec 19 04:04:22 2021
// ----------------------------------------------------------------------------
SmartHLS Summary Report for Project: sobel_part3.
Table of Contents
1. RTL Interface
2. Scheduling Result
3. Pipeline Result
4. Memory Usage
5. Accelerator Information
6. Resource Binding with Adaptive Latency
====== 1. RTL Interface ======
+-------------------------------------------------------------------------------------------+
| RTL Interface Generated by SmartHLS |
+-------------+-------------------+-------------------+------------------+------------------+
| C++ Name | Interface Type | Signal Name | Signal Bit-width | Signal Direction |
+-------------+-------------------+-------------------+------------------+------------------+
| | Control | clk | 1 | input |
| | | finish | 1 | output |
| | | ready | 1 | output |
| | | reset | 1 | input |
| | | start | 1 | input |
+-------------+-------------------+-------------------+------------------+------------------+
| input_fifo | Input AXI Stream | input_fifo_ready | 1 | output |
| | | input_fifo_valid | 1 | input |
| | | input_fifo | 8 | input |
+-------------+-------------------+-------------------+------------------+------------------+
| output_fifo | Output AXI Stream | output_fifo_ready | 1 | input |
| | | output_fifo_valid | 1 | output |
| | | output_fifo | 8 | output |
+-------------+-------------------+-------------------+------------------+------------------+
The Verilog top-level module ports that are not listed in the above table are unused. Please tie the unused input ports to 0.
====== 2. Scheduling Result ======
Please use SmartHLS's schedule viewer to examine the schedule.
Basic Block Latencies:
+---------------------------------------------+
| Function: sobel_filter (pipelined function) |
+---------------------+-----------------------+
| Basic Block | Cycle Latency |
+---------------------+-----------------------+
| %init.check | 12 |
+---------------------+-----------------------+
====== 3. Pipeline Result ======
+--------------+--------------+-------------+-------------------------+---------------------+-----------------+-----------------+---------+
| Label | Function | Basic Block | Location in Source Code | Initiation Interval | Pipeline Length | Iteration Count | Latency |
+--------------+--------------+-------------+-------------------------+---------------------+-----------------+-----------------+---------+
| sobel_filter | sobel_filter | %init.check | line 12 of sobel.cpp | 1 | 12 | n/a | n/a |
+--------------+--------------+-------------+-------------------------+---------------------+-----------------+-----------------+---------+
====== 4. Memory Usage ======
+---------------------------------------------------------------------------------------------------------------------------------------+
| Local Memories |
+----------------------------------------------------+-----------------------+-----------------------+-------------+------------+-------+
| Name | Accessing Function(s) | Type | Size [Bits] | Data Width | Depth |
+----------------------------------------------------+-----------------------+-----------------------+-------------+------------+-------+
| sobel_filter_i | sobel_filter | Register | 32 | 32 | 1 |
| sobel_filter_j | sobel_filter | Register | 32 | 32 | 1 |
| sobel_filter_line_buffer_window_a0_a1 | sobel_filter | Register | 8 | 8 | 1 |
| sobel_filter_line_buffer_window_a0_a2 | sobel_filter | Register | 8 | 8 | 1 |
| sobel_filter_line_buffer_window_a1_a1 | sobel_filter | Register | 8 | 8 | 1 |
| sobel_filter_line_buffer_window_a1_a2 | sobel_filter | Register | 8 | 8 | 1 |
| sobel_filter_line_buffer_window_a2_a1 | sobel_filter | Register | 8 | 8 | 1 |
| sobel_filter_line_buffer_window_a2_a2 | sobel_filter | Register | 8 | 8 | 1 |
| sobel_filter_line_buffer_prev_row_index | sobel_filter | Register | 32 | 32 | 1 |
| sobel_filter_line_buffer_prev_row_a0_a0 | sobel_filter | RAM | 4096 | 8 | 512 |
| sobel_filter_line_buffer_prev_row_a1_a0 | sobel_filter | RAM | 4096 | 8 | 512 |
| sobel_filter_count | sobel_filter | Register | 32 | 32 | 1 |
| init_flag_ZGVZ12sobel_filterRN3hls4FIFOIhLb0EEES2_ | sobel_filter | Register (Write-Only) | 1 | 1 | 1 |
+----------------------------------------------------+-----------------------+-----------------------+-------------+------------+-------+
+-------------------------+
| Local Constant Memories |
+-------------------------+
| None |
+-------------------------+
+-----------------------+
| Shared Local Memories |
+-----------------------+
| None |
+-----------------------+
+------------------+
| Aliased Memories |
+------------------+
| None |
+------------------+
+-------------------------------------------------------------------------------------+
| I/O Memories |
+-------------+-----------------------+------------+-------------+------------+-------+
| Name | Accessing Function(s) | Type | Size [Bits] | Data Width | Depth |
+-------------+-----------------------+------------+-------------+------------+-------+
| input_fifo | sobel_filter | FIFO (REG) | 0 | 8 | 0 |
| output_fifo | sobel_filter | FIFO (REG) | 0 | 8 | 0 |
+-------------+-----------------------+------------+-------------+------------+-------+
====== 5. Accelerator Information ======
No accelerator function is generated.
====== 6. Resource Binding with Adaptive Latency ======
Binding to resource with adaptive latency is disabled.
You can enable this feature by setting config parameter 'ADAPTIVE_LATENCY_BINDING' to 1.
// ----------------------------------------------------------------------------
// Smart High-Level Synthesis Tool Version 2021.2
// Copyright (c) 2015-2021 Microchip Technology Inc. All Rights Reserved.
// For support, please contact: smarthls@microchip.com
// Date: Sat Dec 18 03:58:32 2021
// ----------------------------------------------------------------------------
SmartHLS Summary Report for Project: sobel_part3.
Table of Contents
1. RTL Interface
2. Scheduling Result
3. Pipeline Result
4. Memory Usage
5. Accelerator Information
6. Resource Binding with Adaptive Latency
====== 1. RTL Interface ======
+-------------------------------------------------------------------------------------------+
| RTL Interface Generated by SmartHLS |
+-------------+-------------------+-------------------+------------------+------------------+
| C++ Name | Interface Type | Signal Name | Signal Bit-width | Signal Direction |
+-------------+-------------------+-------------------+------------------+------------------+
| | Control | clk | 1 | input |
| | | finish | 1 | output |
| | | ready | 1 | output |
| | | reset | 1 | input |
| | | start | 1 | input |
+-------------+-------------------+-------------------+------------------+------------------+
| input_fifo | Input AXI Stream | input_fifo_ready | 1 | output |
| | | input_fifo_valid | 1 | input |
| | | input_fifo | 8 | input |
+-------------+-------------------+-------------------+------------------+------------------+
| output_fifo | Output AXI Stream | output_fifo_ready | 1 | input |
| | | output_fifo_valid | 1 | output |
| | | output_fifo | 8 | output |
+-------------+-------------------+-------------------+------------------+------------------+
The Verilog top-level module ports that are not listed in the above table are unused. Please tie the unused input ports to 0.
====== 2. Scheduling Result ======
Please use SmartHLS's schedule viewer to examine the schedule.
Basic Block Latencies:
+---------------------------------------------+
| Function: sobel_filter (pipelined function) |
+---------------------+-----------------------+
| Basic Block | Cycle Latency |
+---------------------+-----------------------+
| %init.check | 7 |
+---------------------+-----------------------+
====== 3. Pipeline Result ======
+--------------+--------------+-------------+-------------------------+---------------------+-----------------+-----------------+---------+
| Label | Function | Basic Block | Location in Source Code | Initiation Interval | Pipeline Length | Iteration Count | Latency |
+--------------+--------------+-------------+-------------------------+---------------------+-----------------+-----------------+---------+
| sobel_filter | sobel_filter | %init.check | line 12 of sobel.cpp | 1 | 7 | n/a | n/a |
+--------------+--------------+-------------+-------------------------+---------------------+-----------------+-----------------+---------+
====== 4. Memory Usage ======
+---------------------------------------------------------------------------------------------------------------------------------------+
| Local Memories |
+----------------------------------------------------+-----------------------+-----------------------+-------------+------------+-------+
| Name | Accessing Function(s) | Type | Size [Bits] | Data Width | Depth |
+----------------------------------------------------+-----------------------+-----------------------+-------------+------------+-------+
| sobel_filter_i | sobel_filter | Register | 32 | 32 | 1 |
| sobel_filter_j | sobel_filter | Register | 32 | 32 | 1 |
| sobel_filter_line_buffer_window_a0_a1 | sobel_filter | Register | 8 | 8 | 1 |
| sobel_filter_line_buffer_window_a0_a2 | sobel_filter | Register | 8 | 8 | 1 |
| sobel_filter_line_buffer_window_a1_a1 | sobel_filter | Register | 8 | 8 | 1 |
| sobel_filter_line_buffer_window_a1_a2 | sobel_filter | Register | 8 | 8 | 1 |
| sobel_filter_line_buffer_window_a2_a1 | sobel_filter | Register | 8 | 8 | 1 |
| sobel_filter_line_buffer_window_a2_a2 | sobel_filter | Register | 8 | 8 | 1 |
| sobel_filter_line_buffer_prev_row_index | sobel_filter | Register | 32 | 32 | 1 |
| sobel_filter_line_buffer_prev_row_a0_a0 | sobel_filter | RAM | 4096 | 8 | 512 |
| sobel_filter_line_buffer_prev_row_a1_a0 | sobel_filter | RAM | 4096 | 8 | 512 |
| sobel_filter_count | sobel_filter | Register | 32 | 32 | 1 |
| init_flag_ZGVZ12sobel_filterRN3hls4FIFOIhLb0EEES2_ | sobel_filter | Register (Write-Only) | 1 | 1 | 1 |
+----------------------------------------------------+-----------------------+-----------------------+-------------+------------+-------+
+-------------------------+
| Local Constant Memories |
+-------------------------+
| None |
+-------------------------+
+-----------------------+
| Shared Local Memories |
+-----------------------+
| None |
+-----------------------+
+------------------+
| Aliased Memories |
+------------------+
| None |
+------------------+
+-------------------------------------------------------------------------------------+
| I/O Memories |
+-------------+-----------------------+------------+-------------+------------+-------+
| Name | Accessing Function(s) | Type | Size [Bits] | Data Width | Depth |
+-------------+-----------------------+------------+-------------+------------+-------+
| input_fifo | sobel_filter | FIFO (REG) | 0 | 8 | 0 |
| output_fifo | sobel_filter | FIFO (REG) | 0 | 8 | 0 |
+-------------+-----------------------+------------+-------------+------------+-------+
====== 5. Accelerator Information ======
No accelerator function is generated.
====== 6. Resource Binding with Adaptive Latency ======
Binding to resource with adaptive latency is disabled.
You can enable this feature by setting config parameter 'ADAPTIVE_LATENCY_BINDING' to 1.
==================================================================
===== Summary Report for RTL Simulation and FPGA Synthesis =====
==================================================================
Project name: sobel_part3
FPGA Vendor: MICROSEMI
Device Family: SmartFusion2
Device: M2S010-VF256
Table of Contents
1. Simulation Cycle Latency
2. Timing Result
3. Resource Usage
====== 1. Simulation Cycle Latency ======
Number of calls: 262,658
Cycle latency: 262,667
SW/HW co-simulation: PASS
====== 2. Timing Result ======
+--------------+---------------+-------------+-------------+----------+-------------+
| Clock Domain | Target Period | Target Fmax | Worst Slack | Period | Fmax |
+--------------+---------------+-------------+-------------+----------+-------------+
| clk | 10.000 ns | 100.000 MHz | 5.076 ns | 4.924 ns | 203.087 MHz |
+--------------+---------------+-------------+-------------+----------+-------------+
The reported Fmax is for the HLS core in isolation (from Libero's post-place-and-route timing analysis).
When the HLS core is integrated into a larger system, the system Fmax may be lower depending on the critical path of the system.
====== 3. Resource Usage ======
+--------------------------+-----------------+-------+------------+
| Resource Type | Used | Total | Percentage |
+--------------------------+-----------------+-------+------------+
| Fabric + Interface 4LUT* | 453 + 288 = 741 | 12084 | 6.13 |
| Fabric + Interface DFF* | 378 + 288 = 666 | 12084 | 5.51 |
| I/O Register | 0 | 414 | 0.00 |
| User I/O | 0 | 138 | 0.00 |
| RAM64x18 | 8 | 22 | 36.36 |
| RAM1K18 | 0 | 21 | 0.00 |
| MACC | 0 | 22 | 0.00 |
+--------------------------+-----------------+-------+------------+
* Interface 4LUTs and DFFs are occupied due to the uses of MACC, RAM1K18, and RAM64x18.
Number of interface 4LUTs/DFFs = (36 * #.MACC) + (36 * #.RAM1K18) + (36 * #.RAM64x18) = (36 * 0) + (36 * 0) + (36 * 8) = 288.
#include <hls/image_processing.hpp>
#include <hls/streaming.hpp>
void sobel_filter(FIFO<unsigned char> &input_fifo,
FIFO<unsigned char> &output_fifo)
static LineBuffer<unsigned char, WIDTH, 3> line_buffer;
でできるようだ。line_buffer.ShiftInPixel(input_pixel);
このように行われている。int pixel = line_buffer.window[m + 1][n + 1];
// Write input pixels and run the hardware model.
for (int i = 0; i < HEIGHT; i++) {
for (int j = 0; j < WIDTH; j++) {
input_fifo.write(elaine_512_input[i][j]);
sobel_filter(input_fifo, output_fifo);
}
}
==================================================================
===== Summary Report for RTL Simulation and FPGA Synthesis =====
==================================================================
Project name: sobel_part2
FPGA Vendor: MICROSEMI
Device Family: SmartFusion2
Device: M2S010-VF256
Table of Contents
1. Simulation Cycle Latency
2. Timing Result
3. Resource Usage
====== 1. Simulation Cycle Latency ======
Number of calls: 1
Cycle latency: 1,040,413
SW/HW co-simulation: PASS
====== 2. Timing Result ======
+--------------+---------------+-------------+-------------+----------+-------------+
| Clock Domain | Target Period | Target Fmax | Worst Slack | Period | Fmax |
+--------------+---------------+-------------+-------------+----------+-------------+
| clk | 10.000 ns | 100.000 MHz | 6.151 ns | 3.849 ns | 259.808 MHz |
+--------------+---------------+-------------+-------------+----------+-------------+
The reported Fmax is for the HLS core in isolation (from Libero's post-place-and-route timing analysis).
When the HLS core is integrated into a larger system, the system Fmax may be lower depending on the critical path of the system.
====== 3. Resource Usage ======
+--------------------------+---------------+-------+------------+
| Resource Type | Used | Total | Percentage |
+--------------------------+---------------+-------+------------+
| Fabric + Interface 4LUT* | 772 + 0 = 772 | 12084 | 6.39 |
| Fabric + Interface DFF* | 533 + 0 = 533 | 12084 | 4.41 |
| I/O Register | 0 | 414 | 0.00 |
| User I/O | 0 | 138 | 0.00 |
| RAM64x18 | 0 | 22 | 0.00 |
| RAM1K18 | 0 | 21 | 0.00 |
| MACC | 0 | 22 | 0.00 |
+--------------------------+---------------+-------+------------+
* Interface 4LUTs and DFFs are occupied due to the uses of MACC, RAM1K18, and RAM64x18.
Number of interface 4LUTs/DFFs = (36 * #.MACC) + (36 * #.RAM1K18) + (36 * #.RAM64x18) = (36 * 0) + (36 * 0) + (36 * 0) = 0.
を追加した。#pragma HLS loop pipeline
// ----------------------------------------------------------------------------
// Smart High-Level Synthesis Tool Version 2021.2
// Copyright (c) 2015-2021 Microchip Technology Inc. All Rights Reserved.
// For support, please contact: smarthls@microchip.com
// Date: Tue Dec 14 04:10:28 2021
// ----------------------------------------------------------------------------
SmartHLS Summary Report for Project: sobel_part2.
Table of Contents
1. RTL Interface
2. Scheduling Result
3. Pipeline Result
4. Memory Usage
5. Accelerator Information
6. Resource Binding with Adaptive Latency
====== 1. RTL Interface ======
+------------------------------------------------------------------------------------+
| RTL Interface Generated by SmartHLS |
+----------+----------------+------------------+------------------+------------------+
| C++ Name | Interface Type | Signal Name | Signal Bit-width | Signal Direction |
+----------+----------------+------------------+------------------+------------------+
| | Control | clk | 1 | input |
| | | finish | 1 | output |
| | | ready | 1 | output |
| | | reset | 1 | input |
| | | start | 1 | input |
+----------+----------------+------------------+------------------+------------------+
| in | Memory | in_address_a | 18 | output |
| | | in_address_b | 18 | output |
| | | in_clken | 1 | output |
| | | in_read_data_a | 8 | input |
| | | in_read_data_b | 8 | input |
| | | in_read_en_a | 1 | output |
| | | in_read_en_b | 1 | output |
+----------+----------------+------------------+------------------+------------------+
| out | Memory | out_address_a | 18 | output |
| | | out_address_b | 18 | output |
| | | out_clken | 1 | output |
| | | out_write_data_a | 8 | output |
| | | out_write_data_b | 8 | output |
| | | out_write_en_a | 1 | output |
| | | out_write_en_b | 1 | output |
+----------+----------------+------------------+------------------+------------------+
The Verilog top-level module ports that are not listed in the above table are unused. Please tie the unused input ports to 0.
====== 2. Scheduling Result ======
Please use SmartHLS's schedule viewer to examine the schedule.
Basic Block Latencies:
+-------------------------------------------------+
| Function: sobel_filter (non-pipelined function) |
+-----------------------+-------------------------+
| Basic Block | Cycle Latency |
+-----------------------+-------------------------+
| %for.end53 | 1 |
| %entry | 1 |
| %for.body | 11 |
+-----------------------+-------------------------+
====== 3. Pipeline Result ======
+-------------------------+--------------+-------------+-------------------------+---------------------+-----------------+-----------------+---------+
| Label | Function | Basic Block | Location in Source Code | Initiation Interval | Pipeline Length | Iteration Count | Latency |
+-------------------------+--------------+-------------+-------------------------+---------------------+-----------------+-----------------+---------+
| for_loop_sobel_cpp_20_5 | sobel_filter | %for.body | line 20 of sobel.cpp | 4 | 11 | 260100 | 1040407 |
+-------------------------+--------------+-------------+-------------------------+---------------------+-----------------+-----------------+---------+
====== 4. Memory Usage ======
+----------------+
| Local Memories |
+----------------+
| None |
+----------------+
+-------------------------+
| Local Constant Memories |
+-------------------------+
| None |
+-------------------------+
+-----------------------+
| Shared Local Memories |
+-----------------------+
| None |
+-----------------------+
+------------------+
| Aliased Memories |
+------------------+
| None |
+------------------+
+------------------------------------------------------------------------+
| I/O Memories |
+------+-----------------------+------+-------------+------------+-------+
| Name | Accessing Function(s) | Type | Size [Bits] | Data Width | Depth |
+------+-----------------------+------+-------------+------------+-------+
| in | sobel_filter | ROM | 0 | 8 | 0 |
| out | sobel_filter | RAM | 0 | 8 | 0 |
+------+-----------------------+------+-------------+------------+-------+
====== 5. Accelerator Information ======
No accelerator function is generated.
====== 6. Resource Binding with Adaptive Latency ======
Binding to resource with adaptive latency is disabled.
You can enable this feature by setting config parameter 'ADAPTIVE_LATENCY_BINDING' to 1.
を書くそうだ。それが、sobel フィルタ・チュートリアルの part2 なので、早速、sobel_part2 プロジェクトを作成する。#pragma HLS loop pipeline
PASS!
make[1]: Leaving directory '/cygdrive/c/Users/marse/Documents/SmartHLS/Sobel_filter/sobel_part1'
make[1]: Entering directory '/cygdrive/c/Users/marse/Documents/SmartHLS/Sobel_filter/sobel_part1'
Number of calls: 1
Cycle latency: 3,392,549
SW/HW co-simulation: PASS
make[1]: Leaving directory '/cygdrive/c/Users/marse/Documents/SmartHLS/Sobel_filter/sobel_part1'
06:12:41 Build Finished (took 1m:12s.115ms)
==================================================================
===== Summary Report for RTL Simulation and FPGA Synthesis =====
==================================================================
Project name: sobel_part1
FPGA Vendor: MICROSEMI
Device Family: SmartFusion2
Device: M2S010-VF256
Table of Contents
1. Simulation Cycle Latency
2. Timing Result
3. Resource Usage
====== 1. Simulation Cycle Latency ======
Number of calls: 1
Cycle latency: 3,392,549
SW/HW co-simulation: PASS
====== 2. Timing Result ======
+--------------+---------------+-------------+-------------+----------+-------------+
| Clock Domain | Target Period | Target Fmax | Worst Slack | Period | Fmax |
+--------------+---------------+-------------+-------------+----------+-------------+
| clk | 10.000 ns | 100.000 MHz | 6.457 ns | 3.543 ns | 282.247 MHz |
+--------------+---------------+-------------+-------------+----------+-------------+
The reported Fmax is for the HLS core in isolation (from Libero's post-place-and-route timing analysis).
When the HLS core is integrated into a larger system, the system Fmax may be lower depending on the critical path of the system.
====== 3. Resource Usage ======
+--------------------------+---------------+-------+------------+
| Resource Type | Used | Total | Percentage |
+--------------------------+---------------+-------+------------+
| Fabric + Interface 4LUT* | 685 + 0 = 685 | 12084 | 5.67 |
| Fabric + Interface DFF* | 430 + 0 = 430 | 12084 | 3.56 |
| I/O Register | 0 | 414 | 0.00 |
| User I/O | 0 | 138 | 0.00 |
| RAM64x18 | 0 | 22 | 0.00 |
| RAM1K18 | 0 | 21 | 0.00 |
| MACC | 0 | 22 | 0.00 |
+--------------------------+---------------+-------+------------+
* Interface 4LUTs and DFFs are occupied due to the uses of MACC, RAM1K18, and RAM64x18.
Number of interface 4LUTs/DFFs = (36 * #.MACC) + (36 * #.RAM1K18) + (36 * #.RAM64x18) = (36 * 0) + (36 * 0) + (36 * 0) = 0.
[LegupConfig.cpp:2173: checkValidPart] Error: Could not find SmartFusion2 part number: 'M2S010-VFG256'
[LegupConfig.cpp:2173: checkValidPart] Error: SmartHLS has exited due to an error. Please contact smarthls@microchip.com for more details.
// ----------------------------------------------------------------------------
// Smart High-Level Synthesis Tool Version 2021.2
// Copyright (c) 2015-2021 Microchip Technology Inc. All Rights Reserved.
// For support, please contact: smarthls@microchip.com
// Date: Fri Dec 10 04:22:39 2021
// ----------------------------------------------------------------------------
SmartHLS Summary Report for Project: sobel_part1.
Table of Contents
1. RTL Interface
2. Scheduling Result
3. Pipeline Result
4. Memory Usage
5. Accelerator Information
6. Resource Binding with Adaptive Latency
====== 1. RTL Interface ======
+------------------------------------------------------------------------------------+
| RTL Interface Generated by SmartHLS |
+----------+----------------+------------------+------------------+------------------+
| C++ Name | Interface Type | Signal Name | Signal Bit-width | Signal Direction |
+----------+----------------+------------------+------------------+------------------+
| | Control | clk | 1 | input |
| | | finish | 1 | output |
| | | ready | 1 | output |
| | | reset | 1 | input |
| | | start | 1 | input |
+----------+----------------+------------------+------------------+------------------+
| in | Memory | in_address_a | 18 | output |
| | | in_address_b | 18 | output |
| | | in_clken | 1 | output |
| | | in_read_data_a | 8 | input |
| | | in_read_data_b | 8 | input |
| | | in_read_en_a | 1 | output |
| | | in_read_en_b | 1 | output |
+----------+----------------+------------------+------------------+------------------+
| out | Memory | out_address_a | 18 | output |
| | | out_address_b | 18 | output |
| | | out_clken | 1 | output |
| | | out_write_data_a | 8 | output |
| | | out_write_data_b | 8 | output |
| | | out_write_en_a | 1 | output |
| | | out_write_en_b | 1 | output |
+----------+----------------+------------------+------------------+------------------+
The Verilog top-level module ports that are not listed in the above table are unused. Please tie the unused input ports to 0.
====== 2. Scheduling Result ======
Please use SmartHLS's schedule viewer to examine the schedule.
Basic Block Latencies:
+-------------------------------------------------+
| Function: sobel_filter (non-pipelined function) |
+--------------------------------+----------------+
| Basic Block | Cycle Latency |
+--------------------------------+----------------+
| %entry | 1 |
| %for.cond1.preheader | 1 |
| %for.body3 | 2 |
| %for.body3.for.inc54_crit_edge | 1 |
| %for.cond14.preheader | 9 |
| %for.inc54 | 2 |
| %for.inc57 | 1 |
| %for.end59 | 1 |
+--------------------------------+----------------+
====== 3. Pipeline Result ======
No pipeline is generated.
====== 4. Memory Usage ======
+----------------+
| Local Memories |
+----------------+
| None |
+----------------+
+-------------------------+
| Local Constant Memories |
+-------------------------+
| None |
+-------------------------+
+-----------------------+
| Shared Local Memories |
+-----------------------+
| None |
+-----------------------+
+------------------+
| Aliased Memories |
+------------------+
| None |
+------------------+
+------------------------------------------------------------------------+
| I/O Memories |
+------+-----------------------+------+-------------+------------+-------+
| Name | Accessing Function(s) | Type | Size [Bits] | Data Width | Depth |
+------+-----------------------+------+-------------+------------+-------+
| in | sobel_filter | ROM | 0 | 8 | 0 |
| out | sobel_filter | RAM | 0 | 8 | 0 |
+------+-----------------------+------+-------------+------------+-------+
====== 5. Accelerator Information ======
No accelerator function is generated.
====== 6. Resource Binding with Adaptive Latency ======
Binding to resource with adaptive latency is disabled.
You can enable this feature by setting config parameter 'ADAPTIVE_LATENCY_BINDING' to 1.
-- ----------------------------------------------------------------------------
-- Smart High-Level Synthesis Tool Version 2021.2
-- Copyright (c) 2015-2021 Microchip Technology Inc. All Rights Reserved.
-- For support, please contact: smarthls@microchip.com
-- Date: Fri Dec 10 04:22:39 2021
-- ----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
library work;
use work.legup_types_pkg.all;
entity sobel_filter_top_vhdl is
port (
i_clk : in std_logic;
i_reset : in std_logic;
i_start : in std_logic;
o_ready : out std_logic;
o_finish : out std_logic;
o_in_clken : out std_logic;
o_in_read_en_a : out std_logic;
o_in_address_a : out std_logic_vector(17 downto 0);
i_in_read_data_a : in std_logic_vector(7 downto 0);
o_in_read_en_b : out std_logic;
o_in_address_b : out std_logic_vector(17 downto 0);
i_in_read_data_b : in std_logic_vector(7 downto 0);
o_out_clken : out std_logic;
o_out_write_en_a : out std_logic;
o_out_write_data_a : out std_logic_vector(7 downto 0);
o_out_read_en_a : out std_logic;
o_out_address_a : out std_logic_vector(17 downto 0);
i_out_read_data_a : in std_logic_vector(7 downto 0);
o_out_write_en_b : out std_logic;
o_out_write_data_b : out std_logic_vector(7 downto 0);
o_out_read_en_b : out std_logic;
o_out_address_b : out std_logic_vector(17 downto 0);
i_out_read_data_b : in std_logic_vector(7 downto 0)
);
end sobel_filter_top_vhdl;
architecture behavior of sobel_filter_top_vhdl is
component sobel_filter_top
port (
clk : in std_logic;
reset : in std_logic;
start : in std_logic;
ready : out std_logic;
finish : out std_logic;
in_clken : out std_logic;
in_read_en_a : out std_logic;
in_address_a : out std_logic_vector(17 downto 0);
in_read_data_a : in std_logic_vector(7 downto 0);
in_read_en_b : out std_logic;
in_address_b : out std_logic_vector(17 downto 0);
in_read_data_b : in std_logic_vector(7 downto 0);
out_clken : out std_logic;
out_write_en_a : out std_logic;
out_write_data_a : out std_logic_vector(7 downto 0);
out_read_en_a : out std_logic;
out_address_a : out std_logic_vector(17 downto 0);
out_read_data_a : in std_logic_vector(7 downto 0);
out_write_en_b : out std_logic;
out_write_data_b : out std_logic_vector(7 downto 0);
out_read_en_b : out std_logic;
out_address_b : out std_logic_vector(17 downto 0);
out_read_data_b : in std_logic_vector(7 downto 0)
);
end component;
begin
sobel_filter_top_inst : sobel_filter_top
port map (
clk => i_clk,
reset => i_reset,
start => i_start,
ready => o_ready,
finish => o_finish,
in_clken => o_in_clken,
in_read_en_a => o_in_read_en_a,
in_address_a => o_in_address_a,
in_read_data_a => i_in_read_data_a,
in_read_en_b => o_in_read_en_b,
in_address_b => o_in_address_b,
in_read_data_b => i_in_read_data_b,
out_clken => o_out_clken,
out_write_en_a => o_out_write_en_a,
out_write_data_a => o_out_write_data_a,
out_read_en_a => o_out_read_en_a,
out_address_a => o_out_address_a,
out_read_data_a => i_out_read_data_a,
out_write_en_b => o_out_write_en_b,
out_write_data_b => o_out_write_data_b,
out_read_en_b => o_out_read_en_b,
out_address_b => o_out_address_b,
out_read_data_b => i_out_read_data_b
);
end behavior;
で引数が 2 次元配列 なので、sobel_part1.vhd がメモリ・アクセスになっているようだが、2 ポートあるのはなぜだろうか？void sobel_filter(unsigned char in[HEIGHT][WIDTH],
unsigned char out[HEIGHT][WIDTH]);
がある。これは、”Zynq UltraScale+ MPSoC TRM 457 UG1085 (v1.4) 2017 年 2 月 2 日”の”表 22‐29: I2C CLK の取得”の様に設定しているものと思われる。XIicPs_SetSClk(&iic_cam, IIC_SCLK_RATE);
// display_port_appn.cpp
// 2021/12/06 by marsee
//
#include <stdio.h>
#include <stdlib.h>
#include <stdint.h>
#include <unistd.h>
#include "xgaussian_filter_axis.h"
#include "xmedian_filter_axis.h"
#include "xsobel_filter_axis.h"
int main(){
XGaussian_filter_axis gfilter_ap;
XMedian_filter_axis mfilter_ap;
XSobel_filter_axis sfilter_ap;
volatile unsigned int *udmabuf4_buf;
int udmabuf4_fd, fd_phys_addr;
char attr[1024];
unsigned long phys_addr;
int Xdma_status;
int i;
// udmabuf4
udmabuf4_fd = open("/dev/udmabuf4", O_RDWR); // frame_buffer, The chache is enabled.
if (udmabuf4_fd == -1){
fprintf(stderr, "/dev/udmabuf4 open error\n");
exit(-1);
}
udmabuf4_buf = (volatile unsigned int *)mmap(NULL, 4096, PROT_READ|PROT_WRITE, MAP_SHARED, udmabuf4_fd, 0);
if (!udmabuf4_buf){
fprintf(stderr, "udmabuf4_buf mmap error\n");
exit(-1);
}
// phys_addr of udmabuf4
fd_phys_addr = open("/sys/class/u-dma-buf/udmabuf4/phys_addr", O_RDONLY);
if (fd_phys_addr == -1){
fprintf(stderr, "/sys/class/u-dma-buf/udmabuf4/phys_addr open error\n");
exit(-1);
}
read(fd_phys_addr, attr, 1024);
sscanf(attr, "%lx", &phys_addr);
close(fd_phys_addr);
printf("phys_addr = %x\n", (int)phys_addr);
return(0);
}
# Makefile(display_port_appn)
# Referred to http://www.ie.u-ryukyu.ac.jp/~e085739/c.makefile.tuts.html
PROGRAM = display_port_appn
OBJS = display_port_appn.o xgaussian_filter_axis_linux.o xgaussian_filter_axis.o xmedian_filter_axis_linux.o xmedian_filter_axis.o xsobel_filter_axis_linux.o xsobel_filter_axis.o
CC = gcc
CFLAGS = -Wall -O2
.SUFFIXES: .c .o
.PHONY: all
all: display_port_appn
display_port_appn: $(OBJS)
$(CC) -Wall -o $@ $(OBJS)
.c.o:
$(CC) $(CFLAGS) -c $<
.PHONY: clean
clean:
$(RM) $(PROGRAM) $(OBJS)
が表示された。成功だ。phys_addr = 70600000
[ 36.166845] systemd-journald[150]: File /var/log/journal/fa5ba2ddbe3544a08d55124c9fe30f95/user-1000.journal corrupted or uncleanly shut down, renaming and replacing.
[ 83.274161] fpga_manager fpga0: writing kria_pcam.bin to Xilinx ZynqMP FPGA Manager
[ 83.751378] OF: overlay: WARNING: memory leak will occur if overlay removed, property: /fpga-full/firmware-name
[ 137.382921] fclkcfg: loading out-of-tree module taints kernel.
[ 137.390050] zynqmp_clk_divider_set_rate() set divider failed for pl0_ref_div1, ret = -13
[ 137.398320] fclkcfg axi:fclk0: driver version : 1.7.2
[ 137.403376] fclkcfg axi:fclk0: device name : axi:fclk0
[ 137.408771] fclkcfg axi:fclk0: clock name : pl0_ref
[ 137.413995] fclkcfg axi:fclk0: clock rate : 99999999
[ 137.419319] fclkcfg axi:fclk0: clock enabled : 1
[ 137.424028] fclkcfg axi:fclk0: remove rate : 1000000
[ 137.429247] fclkcfg axi:fclk0: remove enable : 0
[ 137.433941] fclkcfg axi:fclk0: driver installed.
[ 154.037650] u-dma-buf udmabuf4: driver version = 3.2.4
[ 154.042851] u-dma-buf udmabuf4: major number = 242
[ 154.047840] u-dma-buf udmabuf4: minor number = 0
[ 154.052632] u-dma-buf udmabuf4: phys address = 0x0000000070600000
[ 154.058900] u-dma-buf udmabuf4: buffer size = 1048576
[ 154.064210] u-dma-buf axi:kria_pcam-udmabuf4: driver installed.
all:
{
[destination_device = pl] design_1_wrapper.bit
}
/dts-v1/;
/ {
fragment@0 {
target-path = "/fpga-full";
__overlay__ {
firmware-name = "kria_pcam.bin";
};
};
};
/dts-v1/;/plugin/;
/ {
fragment@0 {
target-path = "/axi";
__overlay__ {
fclk0 {
compatible = "ikwzm,fclkcfg-0.10.a";
clocks = <&zynqmp_clk 0x47>;
insert-rate = "100000000";
insert-enable = <1>;
remove-rate = "1000000";
remove-enable = <0>;
};
};
};
};
/dts-v1/;/plugin/;
/ {
fragment@0 {
target-path = "/axi";
#address-cells = <2>;
#size-cells = <2>;
__overlay__ {
#address-cells = <2>;
#size-cells = <2>;
axi_intc-uio {
compatible = "generic-uio";
reg = <0x0 0x00A0010000 0x0 0x10000>;
};
axi_vdma-uio {
compatible = "generic-uio";
reg = <0x0 0x00A0020000 0x0 0x10000>;
};
gaussian_filter_axis-uio {
compatible = "generic-uio";
reg = <0x0 0x00A0070000 0x0 0x10000>;
};
median_filter_axis-uio {
compatible = "generic-uio";
reg = <0x0 0x00A0080000 0x0 0x10000>;
};
mipi_csi2_rx_subsyst-uio {
compatible = "generic-uio";
reg = <0x0 0x00A0000000 0x0 0x1000>;
};
sobel_filter_axis-uio {
compatible = "generic-uio";
reg = <0x0 0x00A0060000 0x0 0x10000>;
};
v_demosaic-uio {
compatible = "generic-uio";
reg = <0x0 0x00A0030000 0x0 0x10000>;
};
v_gamma_lut-uio {
compatible = "generic-uio";
reg = <0x0 0x00A0040000 0x0 0x10000>;
};
v_tc-uio {
compatible = "generic-uio";
reg = <0x0 0x00A0050000 0x0 0x10000>;
};
kria_pcam-udmabuf4 {
compatible = "ikwzm,u-dma-buf";
device-name = "udmabuf4";
size = <0x00100000>;
};
};
};
};
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