// xf_resize_axis.h
// 2022/01/30 by marsee
// Vitis_Libraries/vision/L1/examples/resize/を参照している
// https://github.com/Xilinx/Vitis_Libraries/tree/master/vision/L1/examples/resize
// Vitis_Libraries/vision/L1/examples/resize/build/xf_config_params.h を引用
#ifndef _XF_RESIZE_AXIS_
#define _XF_RESIZE_AXIS_
#include "hls_stream.h"
#include "ap_int.h"
#include "common/xf_common.hpp"
#include "ap_axi_sdata.h"
#include "common/xf_infra.hpp"
#include "common/xf_axi_io.hpp"
#include "imgproc/xf_resize.hpp"
#define RGB 1
#define GRAY 0
#define NPxPC XF_NPPC1
#if GRAY
#define TYPE XF_8UC1
#define CHANNELS 1
#define STREAMW 8
#else
#define TYPE XF_8UC3
#define CHANNELS 3
#define STREAMW 32
#endif
/* set the height and weight */
#define WIDTH 1920
#define HEIGHT 1080
#define WIDTH 1920
#define HEIGHT 1080
/* Interpolation type*/
#define INTERPOLATION 1
// 0 - Nearest Neighbor Interpolation
// 1 - Bilinear Interpolation
// 2 - AREA Interpolation
/* Input image Dimensions */
#define WIDTH 1920 // Maximum Input image width
#define HEIGHT 1080 // Maximum Input image height
/* Output image Dimensions */
#define NEWWIDTH 1920 // Maximum output image width
#define NEWHEIGHT 1080 // Maximum output image height
#endif
// xf_resize_axis.cpp
// 2022/01/30 by marsee
// Vitis_Libraries/vision/L1/examples/resize/を参照している
// https://github.com/Xilinx/Vitis_Libraries/tree/master/vision/L1/examples/resize
#include "xf_resize_axis.h"
void resize_accel_axis(AXI_STREAM& _src, AXI_STREAM& _dst,
int32_t in_height, int32_t in_width, int32_t out_height, int32_t out_width){
#pragma HLS INTERFACE mode=s_axilite port=out_width
#pragma HLS INTERFACE mode=s_axilite port=out_height
#pragma HLS INTERFACE mode=s_axilite port=in_width
#pragma HLS INTERFACE mode=s_axilite port=in_height
#pragma HLS INTERFACE mode=s_axilite port=return
#pragma HLS INTERFACE mode=axis register_mode=both port=_src register
#pragma HLS INTERFACE mode=axis register_mode=both port=_dst register
xf::cv::Mat<TYPE, HEIGHT, WIDTH, NPxPC> img_in(in_height, in_width);
xf::cv::Mat<TYPE, NEWHEIGHT, NEWWIDTH, NPxPC> img_out(out_height, out_width);
#pragma HLS DATAFLOW
xf::cv::AXIvideo2xfMat(_src, img_in);
xf::cv::xf_resize_axis <INTERPOLATION, TYPE, HEIGHT, WIDTH,
NEWHEIGHT, NEWWIDTH, NPxPC, MAXDOWNSCALE> (img_in, img_out);
xf::cv::xfMat2AXIvideo(img_out, _dst);
}
を設定した。-I/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Libraries/vision/L1/include -std=c++0x
ERROR: [HLS 207-812] 'common/xf_common.hpp' file not found (xf_resize_axis/xf_resize_axis.h:11:10) xf_resize_axis:solution1 Jan 31, 2022, 4:17:00 AM
Starting C synthesis ...
/media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis_HLS/2021.2/bin/vitis_hls /media/masaaki/Ubuntu_Disk/Vitis_HLS/ZYBO_Z7_20/2021.2/xf_resize_axis/solution1/csynth.tcl
INFO: Applying HLS Y2K22 patch v1.2 for IP revision
INFO: [HLS 200-10] Running '/media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis_HLS/2021.2/bin/unwrapped/lnx64.o/vitis_hls'
INFO: [HLS 200-10] For user 'masaaki' on host 'masaaki-H110M4-M01' (Linux_x86_64 version 4.15.0-166-generic) on Mon Jan 31 04:16:59 JST 2022
INFO: [HLS 200-10] On os Ubuntu 18.04.6 LTS
INFO: [HLS 200-10] In directory '/media/masaaki/Ubuntu_Disk/Vitis_HLS/ZYBO_Z7_20/2021.2'
WARNING: [HLS 200-40] Environment variable 'C_INCLUDE_PATH' is set to :/usr/local/cuda/include.
Sourcing Tcl script '/media/masaaki/Ubuntu_Disk/Vitis_HLS/ZYBO_Z7_20/2021.2/xf_resize_axis/solution1/csynth.tcl'
INFO: [HLS 200-1510] Running: open_project xf_resize_axis
INFO: [HLS 200-10] Opening project '/media/masaaki/Ubuntu_Disk/Vitis_HLS/ZYBO_Z7_20/2021.2/xf_resize_axis'.
INFO: [HLS 200-1510] Running: set_top resize_accel_axis
INFO: [HLS 200-1510] Running: add_files xf_resize_axis/xf_resize_axis.cpp -cflags -I../../../../../Xilinx_github/Vitis_Libraries/vision/L1/include -std=c++0x
INFO: [HLS 200-10] Adding design file 'xf_resize_axis/xf_resize_axis.cpp' to the project
INFO: [HLS 200-1510] Running: add_files -tb xf_resize_axis/xf_resize_axis_tb.cpp -cflags -I../../../Xilinx_github/Vitis_Libraries/vision/L1/include -I../../../../../../usr/local/include -std=c++0x -Wno-unknown-pragmas -csimflags -Wno-unknown-pragmas
INFO: [HLS 200-10] Adding test bench file 'xf_resize_axis/xf_resize_axis_tb.cpp' to the project
INFO: [HLS 200-1510] Running: open_solution solution1 -flow_target vivado
INFO: [HLS 200-10] Opening solution '/media/masaaki/Ubuntu_Disk/Vitis_HLS/ZYBO_Z7_20/2021.2/xf_resize_axis/solution1'.
INFO: [SYN 201-201] Setting up clock 'default' with a period of 10ns.
INFO: [HLS 200-1611] Setting target device to 'xc7z020-clg400-1'
INFO: [HLS 200-1505] Using flow_target 'vivado'
Resolution: For help on HLS 200-1505 see www.xilinx.com/cgi-bin/docs/rdoc?v=2021.2;t=hls+guidance;d=200-1505.html
INFO: [HLS 200-1510] Running: set_part xc7z020-clg400-1
INFO: [HLS 200-1510] Running: create_clock -period 10 -name default
INFO: [HLS 200-1510] Running: csynth_design
INFO: [HLS 200-111] Finished File checks and directory preparation: CPU user time: 0.02 seconds. CPU system time: 0 seconds. Elapsed time: 0.01 seconds; current allocated memory: 1.125 GB.
INFO: [HLS 200-10] Analyzing design file 'xf_resize_axis/xf_resize_axis.cpp' ...
ERROR: [HLS 207-812] 'common/xf_common.hpp' file not found (xf_resize_axis/xf_resize_axis.h:11:10)
INFO: [HLS 200-111] Finished Command csynth_design CPU user time: 0.25 seconds. CPU system time: 0.06 seconds. Elapsed time: 0.16 seconds; current allocated memory: 0.000 MB.
command 'ap_source' returned error code
while executing
"source /media/masaaki/Ubuntu_Disk/Vitis_HLS/ZYBO_Z7_20/2021.2/xf_resize_axis/solution1/csynth.tcl"
invoked from within
"hls::main /media/masaaki/Ubuntu_Disk/Vitis_HLS/ZYBO_Z7_20/2021.2/xf_resize_axis/solution1/csynth.tcl"
("uplevel" body line 1)
invoked from within
"uplevel 1 hls::main {*}$newargs"
(procedure "hls_proc" line 16)
invoked from within
"hls_proc [info nameofexecutable] $argv"
INFO: [HLS 200-112] Total CPU user time: 2.47 seconds. Total CPU system time: 0.47 seconds. Total elapsed time: 1.86 seconds; peak allocated memory: 1.125 GB.
Finished C synthesis.
// median_filter_axis.c
// 2022/01/29 by marsee
//
#include <stdio.h>
#include "xil_io.h"
#include "xparameters.h"
#include "xmedian_blur_accel_axis.h"
#include "xdma2axis2st.h"
#include "xaxis2dma2st.h"
#include "pict_data.h"
#define FRAME_BUFFER_ADDRESS 0x10000000
#define DMA_DEST_ADDRESS 0x10200000
#define HORIZONTAL_PIXELS 800
#define VERTICAL_LINES 600
int bmp_write(unsigned int addr);
void Xil_DCacheFlush(void);
int main(){
XMedian_blur_accel_axis xmf_axis_ap;
XDma2axis2st xdma2axis_ap;
XAxis2dma2st xaxis2dma_ap;
int inbyte_in;
XMedian_blur_accel_axis_Initialize(&xmf_axis_ap, 0);
XDma2axis2st_Initialize(&xdma2axis_ap, 0);
XAxis2dma2st_Initialize(&xaxis2dma_ap, 0);
XDma2axis2st_Set_y_size(&xdma2axis_ap, (u32)VERTICAL_LINES);
XDma2axis2st_Set_x_size(&xdma2axis_ap, (u32)HORIZONTAL_PIXELS);
XDma2axis2st_Set_sel(&xdma2axis_ap, (u32)0);
XDma2axis2st_Set_in_r(&xdma2axis_ap, (u32)FRAME_BUFFER_ADDRESS);
XMedian_blur_accel_axis_Set_img_width(&xmf_axis_ap, (u32)HORIZONTAL_PIXELS);
XMedian_blur_accel_axis_Set_img_height(&xmf_axis_ap, (u32)VERTICAL_LINES);
XAxis2dma2st_Set_y_size(&xaxis2dma_ap, (u32)VERTICAL_LINES);
XAxis2dma2st_Set_x_size(&xaxis2dma_ap, (u32)HORIZONTAL_PIXELS);
XAxis2dma2st_Set_sel(&xaxis2dma_ap, (u32)0);
XAxis2dma2st_Set_out_r(&xaxis2dma_ap, (u32)DMA_DEST_ADDRESS);
bmp_write(FRAME_BUFFER_ADDRESS);
Xil_DCacheFlush();
XAxis2dma2st_Start(&xaxis2dma_ap);
XMedian_blur_accel_axis_Start(&xmf_axis_ap);
XDma2axis2st_Start(&xdma2axis_ap);
Xil_Out32(XPAR_BITMAP_DISP_CNTRLER_0_BASEADDR, DMA_DEST_ADDRESS);
while(1){
printf("\nPlease input <0> or <1> (<q> : exit) = ");
fflush(stdout);
inbyte_in = inbyte();
printf("%c", inbyte_in);
fflush(stdout);
switch(inbyte_in) {
case '0': //bmp image
XDma2axis2st_Set_sel(&xdma2axis_ap, (u32)0);
XAxis2dma2st_Set_sel(&xaxis2dma_ap, (u32)0);
XAxis2dma2st_Start(&xaxis2dma_ap);
XMedian_blur_accel_axis_Start(&xmf_axis_ap);
XDma2axis2st_Start(&xdma2axis_ap);
break;
case '1': // filter
XDma2axis2st_Set_sel(&xdma2axis_ap, (u32)1);
XAxis2dma2st_Set_sel(&xaxis2dma_ap, (u32)1);
XAxis2dma2st_Start(&xaxis2dma_ap);
XMedian_blur_accel_axis_Start(&xmf_axis_ap);
XDma2axis2st_Start(&xdma2axis_ap);
break;
case 'q': // exit
return(0);
}
}
}
int bmp_write(unsigned int addr){
for(int y=0; y<VERTICAL_LINES; y++){
for(int x=0; x<HORIZONTAL_PIXELS; x++){
Xil_Out32(addr+(y*HORIZONTAL_PIXELS+x)*sizeof(int),
((int)pict_file_array[y][x][2]<<16)+((int)pict_file_array[y][x][1]<<8)+(int)pict_file_array[y][x][0]);
}
}
return(0);
}
set_property IOSTANDARD TMDS_33 [get_ports TMDS_tx_0_B_p_0]
set_property IOSTANDARD TMDS_33 [get_ports TMDS_tx_1_R_p_0]
set_property IOSTANDARD TMDS_33 [get_ports TMDS_tx_2_G_p_0]
set_property IOSTANDARD TMDS_33 [get_ports TMDS_tx_clk_p_0]
set_property PACKAGE_PIN H16 [get_ports TMDS_tx_clk_p_0]
set_property PACKAGE_PIN D19 [get_ports TMDS_tx_0_B_p_0]
set_property PACKAGE_PIN C20 [get_ports TMDS_tx_1_R_p_0]
set_property PACKAGE_PIN B19 [get_ports TMDS_tx_2_G_p_0]
set_false_path -from [get_clocks clk_fpga_0] -to [get_clocks -of_objects [get_pins median_filter_i/bitmap_disp_cntrler_0/inst/dvi_disp_i/BUFR_pixel_clk_io/O]]
set_false_path -from [get_clocks -of_objects [get_pins median_filter_i/bitmap_disp_cntrler_0/inst/dvi_disp_i/BUFR_pixel_clk_io/O]] -to [get_clocks clk_fpga_0]
set_property IOSTANDARD TMDS_33 [get_ports TMDS_tx_0_B_p_0]
set_property IOSTANDARD TMDS_33 [get_ports TMDS_tx_1_R_p_0]
set_property IOSTANDARD TMDS_33 [get_ports TMDS_tx_2_G_p_0]
set_property IOSTANDARD TMDS_33 [get_ports TMDS_tx_clk_p_0]
set_property PACKAGE_PIN H16 [get_ports TMDS_tx_clk_p_0]
set_property PACKAGE_PIN D19 [get_ports TMDS_tx_0_B_p_0]
set_property PACKAGE_PIN C20 [get_ports TMDS_tx_1_R_p_0]
set_property PACKAGE_PIN B19 [get_ports TMDS_tx_2_G_p_0]
// axis2DMA2st.cpp
// for Vitis HLS 2021.2
// 2022/01/24 by marsee
//
#include <ap_int.h>
#include <hls_stream.h>
#include <ap_axi_sdata.h>
#include <stdint.h>
int axis2DMA2st(hls::stream<ap_axis<32,1,1,1> >& ins0, hls::stream<ap_axis<32,1,1,1> >& ins1,
ap_uint<1> sel, int32_t x_size, int32_t y_size, ap_int<32> *out){
#pragma HLS INTERFACE mode=s_axilite port=y_size
#pragma HLS INTERFACE mode=s_axilite port=x_size
#pragma HLS INTERFACE mode=s_axilite port=sel
#pragma HLS INTERFACE mode=axis register_mode=both port=ins1 register
#pragma HLS INTERFACE mode=axis register_mode=both port=ins0 register
#pragma HLS INTERFACE s_axilite port=return
#pragma HLS INTERFACE m_axi depth=480000 port=out offset=slave
ap_axis<32,1,1,1> val;
Loop1 : do { // user が 1 になった時にスタート
#pragma HLS LOOP_TRIPCOUNT min=1 max=1 avg=1
if(sel == 0)
ins0 >> val;
else
ins1 >> val;
} while(val.user == 0);
for(int y=0; y<y_size; y++){
#pragma HLS LOOP_TRIPCOUNT min=600 max=600 avg=600
for(int x=0; x<x_size; x++){
#pragma HLS LOOP_TRIPCOUNT min=800 max=800 avg=800
if(!(y==0 && x==0)){
if(sel == 0)
ins0 >> val;
else
ins1 >> val;
}
out[y*x_size+x] = val.data;
}
}
return(0);
}
// axis2DMA2st_tb.cpp
// for Vitis HLS 2021.2
// 2022/01/24 by marsee
//
#include <iostream>
#include <ap_int.h>
#include <hls_stream.h>
#include <ap_axi_sdata.h>
#include "opencv2/opencv.hpp"
#include "opencv2/imgproc/imgproc.hpp"
#include "opencv2/highgui/highgui.hpp"
#include "opencv2/imgcodecs/imgcodecs.hpp"
#include "pict_data.h"
char OUTPUT_PICT_FILE0[] = "test0.jpg";
char OUTPUT_PICT_FILE1[] = "test1.jpg";
int axis2DMA2st(hls::stream<ap_axis<32,1,1,1> >& ins0, hls::stream<ap_axis<32,1,1,1> >& ins1,
ap_uint<1> sel, int32_t x_size, int32_t y_size, ap_int<32> *out);
int main(){
hls::stream<ap_axis<32,1,1,1> > ins0;
hls::stream<ap_axis<32,1,1,1> > ins1;
ap_axis<32,1,1,1> axisp;
ap_int<32> *wr_pict0, *wr_pict1;
for(int y=0; y<Y_SIZE; y++){
for(int x=0; x<X_SIZE; x++){
axisp.data = (ap_int<32>)pict_file_array[y][x][0] | ((ap_int<32>)pict_file_array[y][x][1])<<8 | ((ap_int<32>)pict_file_array[y][x][2])<<16;
if(y==0 && x==0)
axisp.user = 1;
else
axisp.user = 0;
if(x == X_SIZE-1)
axisp.last = 1;
else
axisp.last = 0;
ins0 << axisp;
ins1 << axisp;
}
}
if((wr_pict0 =(ap_int<32> *)malloc(sizeof(ap_int<32>) * (X_SIZE * Y_SIZE))) == NULL){
fprintf(stderr, "Can't allocate wr_pict0 memory\n");
exit(1);
}
if((wr_pict1 =(ap_int<32> *)malloc(sizeof(ap_int<32>) * (X_SIZE * Y_SIZE))) == NULL){
fprintf(stderr, "Can't allocate wr_pict1 memory\n");
exit(1);
}
axis2DMA2st(ins0, ins1, 0, X_SIZE, Y_SIZE, wr_pict0);
cv::Mat img(Y_SIZE, X_SIZE, CV_8UC3);
cv::Mat_<cv::Vec3b> dst_vec3b = cv::Mat_<cv::Vec3b>(img);
for (int y=0; y<Y_SIZE; y++){
for (int x=0; x<X_SIZE; x++){
ap_int<32> data = wr_pict0[y*X_SIZE+x];
cv::Vec3b pixel;
pixel[0] = data & 0xff; // blue
pixel[1] = (data >> 8) & 0xff; // green
pixel[2] = (data >> 16) & 0xff; // red
dst_vec3b(y,x) = pixel;
}
}
cv::imwrite(OUTPUT_PICT_FILE0, img);
axis2DMA2st(ins0, ins1, 1, X_SIZE, Y_SIZE, wr_pict1);
for (int y=0; y<Y_SIZE; y++){
for (int x=0; x<X_SIZE; x++){
ap_int<32> data = wr_pict1[y*X_SIZE+x];
cv::Vec3b pixel;
pixel[0] = data & 0xff; // blue
pixel[1] = (data >> 8) & 0xff; // green
pixel[2] = (data >> 16) & 0xff; // red
dst_vec3b(y,x) = pixel;
}
}
cv::imwrite(OUTPUT_PICT_FILE1, img);
return(0);
}
を設定した。-I/usr/local/include
を設定した。-L/usr/local/lib -lopencv_core -lopencv_imgcodecs -lopencv_imgproc
// DMA2axis2st.cpp
// for Vitis HLS 2021.2
// 2022/01/21 by marsee
//
#include <ap_int.h>
#include <hls_stream.h>
#include <ap_axi_sdata.h>
int DMA2axis2st(ap_int<32> *in, int sel, int x_size, int y_size,
hls::stream<ap_axis<32,1,1,1> >& outs0, hls::stream<ap_axis<32,1,1,1> >& outs1){
#pragma HLS INTERFACE mode=s_axilite port=return
#pragma HLS INTERFACE mode=axis register_mode=both port=outs1 register
#pragma HLS INTERFACE mode=axis register_mode=both port=outs0 register
#pragma HLS INTERFACE mode=s_axilite port=y_size
#pragma HLS INTERFACE mode=s_axilite port=x_size
#pragma HLS INTERFACE mode=s_axilite port=sel
#pragma HLS INTERFACE mode=m_axi depth=480000 port=in
ap_axis<32,1,1,1> out_val;
for(int y=0; y<y_size; y++){
#pragma HLS LOOP_TRIPCOUNT min=600 max=600 avg=600
for(int x=0; x<x_size; x++){
#pragma HLS LOOP_TRIPCOUNT min=800 max=800 avg=800
out_val.data = in[y*x_size+x];
if(x==0 && y==0)
out_val.user = 1;
else
out_val.user = 0;
if(x == x_size-1)
out_val.last = 1;
else
out_val.last = 0;
if(sel == 0)
outs0 << out_val;
else
outs1 << out_val;
}
}
return(0);
}
// DMA2axis2st_tb.cpp
// for Vitis HLS 2021.2
// 2022/01/21 by marsee
//
#include <ap_int.h>
#include <hls_stream.h>
#include <ap_axi_sdata.h>
#include <iostream>
#include "opencv2/opencv.hpp"
#include "opencv2/imgproc/imgproc.hpp"
#include "opencv2/highgui/highgui.hpp"
#include "opencv2/imgcodecs/imgcodecs.hpp"
#include "pict_data.h"
#define Y_SIZE 600
#define X_SIZE 800
char OUTPUT_PICT_FILE0[] = "test0.jpg";
char OUTPUT_PICT_FILE1[] = "test1.jpg";
int DMA2axis2st(ap_int<32> *in, int sel, int x_size, int y_size,
hls::stream<ap_axis<32,1,1,1> >& outs0, hls::stream<ap_axis<32,1,1,1> >& outs1);
int main(){
hls::stream<ap_axis<32,1,1,1> > outs0;
hls::stream<ap_axis<32,1,1,1> > outs1;
ap_axis<32,1,1,1> axisp;
ap_int<32> *rd_pict;
if((rd_pict =(ap_int<32> *)malloc(sizeof(ap_int<32>) * (X_SIZE * Y_SIZE))) == NULL){
fprintf(stderr, "Can't allocate rd_pict memory\n");
exit(1);
}
for(int y=0; y<Y_SIZE; y++){
for(int x=0; x<X_SIZE; x++){
rd_pict[y*X_SIZE+x] = (int)(pict_file_array[y][x][0]) | ((int)(pict_file_array[y][x][1])<<8) | ((int)(pict_file_array[y][x][2]) <<16);
}
}
DMA2axis2st(rd_pict, 0, X_SIZE, Y_SIZE, outs0, outs1);
cv::Mat img(Y_SIZE, X_SIZE, CV_8UC3);
cv::Mat_<cv::Vec3b> dst_vec3b = cv::Mat_<cv::Vec3b>(img);
for (int y=0; y<Y_SIZE; y++){
for (int x=0; x<X_SIZE; x++){
outs0 >> axisp;
cv::Vec3b pixel;
pixel[0] = axisp.data & 0xff; // blue
pixel[1] = (axisp.data >> 8) & 0xff; // green
pixel[2] = (axisp.data >> 16) & 0xff; // red
dst_vec3b(y,x) = pixel;
}
}
cv::imwrite(OUTPUT_PICT_FILE0, img);
DMA2axis2st(rd_pict, 1, X_SIZE, Y_SIZE, outs0, outs1);
for (int y=0; y<Y_SIZE; y++){
for (int x=0; x<X_SIZE; x++){
outs1 >> axisp;
cv::Vec3b pixel;
pixel[0] = axisp.data & 0xff; // blue
pixel[1] = (axisp.data >> 8) & 0xff; // green
pixel[2] = (axisp.data >> 16) & 0xff; // red
dst_vec3b(y,x) = pixel;
}
}
cv::imwrite(OUTPUT_PICT_FILE1, img);
return(0);
}
を設定した。-I/usr/local/include
を設定した。-L/usr/local/lib -lopencv_core -lopencv_imgcodecs -lopencv_imgproc
int dummy(){
return 0;
}
// pict_header2image.cpp
// 2022/01/21 by marsee
//
#include <iostream>
#include "opencv2/opencv.hpp"
#include "opencv2/imgproc/imgproc.hpp"
#include "opencv2/highgui/highgui.hpp"
#include "opencv2/imgcodecs/imgcodecs.hpp"
#include "pict_data.h"
char OUTPUT_PICT_FILE[] = "test2.jpg";
int main(){
cv::Mat img(Y_SIZE, X_SIZE, CV_8UC3);
cv::Mat_<cv::Vec3b> dst_vec3b = cv::Mat_<cv::Vec3b>(img);
for (int y=0; y<Y_SIZE; y++){
for (int x=0; x<X_SIZE; x++){
cv::Vec3b pixel;
pixel[0] = pict_file_array[y][x][0]; // blue
pixel[1] = pict_file_array[y][x][1]; // green
pixel[2] = pict_file_array[y][x][2]; // red
dst_vec3b(y,x) = pixel;
}
}
cv::imwrite(OUTPUT_PICT_FILE, img);
return(0);
}
を設定した。-I/usr/local/include
を設定した。-L/usr/local/lib -lopencv_core -lopencv_imgcodecs -lopencv_imgproc
int dummy(){
return 0;
}
// pict_header_file.cpp
// 画像を C のヘッダファイルに変換する
// 2022/01/19 by marsee
#include <iostream>
#include <stdlib.h>
#include "opencv2/opencv.hpp"
#include "opencv2/imgproc/imgproc.hpp"
#include "opencv2/highgui/highgui.hpp"
#include "opencv2/imgcodecs/imgcodecs.hpp"
char INPUT_PICT_FILE[] = "test2.jpg";
char OUTPUT_HEADER_FILE[] = "pict_data.h";
int main(){
uint8_t *red, *green, *blue;
FILE *fbmpw;
// 画像ファイルをMat に読み込む
cv::Mat img = cv::imread(INPUT_PICT_FILE);
// ピクセルを入れるメモリをアロケートする
if ((red =(uint8_t *)malloc(sizeof(uint8_t) * (img.rows * img.cols))) == NULL){
fprintf(stderr, "Can't allocate red memory\n");
exit(1);
}
if ((green =(uint8_t *)malloc(sizeof(uint8_t) * (img.rows * img.cols))) == NULL){
fprintf(stderr, "Can't allocate green memory\n");
exit(1);
}
if ((blue =(uint8_t *)malloc(sizeof(uint8_t) * (img.rows * img.cols))) == NULL){
fprintf(stderr, "Can't allocate blue memory\n");
exit(1);
}
cv::Mat_<cv::Vec3b> dst_vec3b = cv::Mat_<cv::Vec3b>(img);
for (int y=0; y<img.rows; y++){
for (int x=0; x<img.cols; x++){
cv::Vec3b pixel;
pixel = dst_vec3b(y,x);
blue[y*img.cols+x] = pixel[0]; // blue
green[y*img.cols+x] = pixel[1]; // green
red[y*img.cols+x] = pixel[2]; // red
}
}
// 画像データのヘッダを画像出力ファイルに書き込む
if ((fbmpw = fopen(OUTPUT_HEADER_FILE, "w")) == NULL){
fprintf(stderr, "Can't open bmp header file\n");
exit(1);
}
fprintf(fbmpw, "// %s\n", OUTPUT_HEADER_FILE);
time_t now = std::time(nullptr);
struct tm* jst = std::localtime(&now);
fprintf(fbmpw, "// %04d/%02d/%02d %02d:%02d:%02d by marsee\n", jst->tm_year+1900, jst->tm_mon+1, jst->tm_mday,
jst->tm_hour, jst->tm_min, jst->tm_sec);
fprintf(fbmpw, "//\n\n");
fprintf(fbmpw, "#define X_SIZE %d\n", img.cols);
fprintf(fbmpw, "#define Y_SIZE %d\n\n", img.rows);
fprintf(fbmpw, "unsigned char pict_file_array[%d][%d][3] = {\n", img.rows, img.cols);
for (int y=0; y<img.rows; y++){
fprintf(fbmpw, "\t{");
for (int x=0; x<img.cols; x++){
if (x != 0)
fprintf(fbmpw, ",");
fprintf(fbmpw, "{%d,%d,%d}", blue[y*img.cols+x], green[y*img.cols+x], red[y*img.cols+x]);
}
if (y == (img.rows-1))
fprintf(fbmpw, "}\n");
else
fprintf(fbmpw, "},\n");
}
fprintf(fbmpw, "\n};");
fclose(fbmpw);
return(0);
}
を設定した。-I/usr/local/include
を設定した。-L/usr/local/lib -lopencv_core -lopencv_imgcodecs -lopencv_imgproc
// xf_median_blur.h
// 2020/03/09 by marsee
// xfopencv/examples/medianblur/xf_median_blur_config.h のコードを引用している
// https://github.com/Xilinx/xfopencv/blob/master/examples/medianblur/xf_median_blur_config.h
// xfopencv/examples/medianblur/xf_config_params.h のコードを引用している
// https://github.com/Xilinx/xfopencv/blob/master/examples/medianblur/xf_config_params.h
// 2022/01/10 : for Vitis Vision Library
#ifndef __XF_MEDIAN_BLUR_H__
#define __XF_MEDIAN_BLUR_H__
#include "hls_stream.h"
#include "ap_int.h"
#include "common/xf_common.hpp"
#include "ap_axi_sdata.h"
#include "common/xf_infra.hpp"
#include "common/xf_axi_io.hpp"
#include "imgproc/xf_median_blur.hpp"
//#include "xf_config_params.hpp"
#define NO 1 // Normal Operation
#define RO 0 // Resource Optimized
#define RGB 1
#define GRAY 0
/* Filter window size*/
#define WINDOW_SIZE 3
/* set the height and weight */
#define WIDTH 1920
#define HEIGHT 1080
#if NO
#define NPxPC XF_NPPC1
#else
#define NPxPC XF_NPPC8
#endif
#if GRAY
#define TYPE XF_8UC1
#define CHANNELS 1
#define STREAMW 8
#else
#define TYPE XF_8UC3
#define CHANNELS 3
#define STREAMW 32
#endif
typedef hls::stream<ap_axiu<STREAMW,1,1,1> > AXI_STREAM;
#endif
// xf_median_blur.cpp
// 2020/03/08 by marsee
// xfopencv/HLS_Use_Model/Standalone_HLS_AXI_Example/xf_ip_accel_app.cpp のコードを引用している
// https://github.com/Xilinx/xfopencv/blob/master/HLS_Use_Model/Standalone_HLS_AXI_Example/xf_ip_accel_app.cpp
// xfopencv/examples/medianblur/xf_median_blur_accel.cpp のコードを引用している
// https://github.com/Xilinx/xfopencv/blob/master/examples/medianblur/xf_median_blur_accel.cpp
// 2022/01/10 : for Vitis Vision Library
#include "xf_median_blur.h"
void median_blur_accel_axis(AXI_STREAM& _src, AXI_STREAM& _dst, int img_height, int img_width){
#pragma HLS INTERFACE mode=s_axilite port=img_width
#pragma HLS INTERFACE mode=s_axilite port=img_height
#pragma HLS INTERFACE mode=s_axilite port=return
#pragma HLS INTERFACE mode=axis register_mode=both port=_src register
#pragma HLS INTERFACE mode=axis register_mode=both port=_dst register
xf::cv::Mat<TYPE, HEIGHT, WIDTH, NPxPC> img_in(img_height, img_width);
xf::cv::Mat<TYPE, HEIGHT, WIDTH, NPxPC> img_out(img_height, img_width);
#pragma HLS DATAFLOW
xf::cv::AXIvideo2xfMat(_src, img_in);
xf::cv::medianBlur <WINDOW_SIZE, XF_BORDER_REPLICATE, TYPE, HEIGHT, WIDTH, NPxPC> (img_in, img_out);
xf::cv::xfMat2AXIvideo(img_out, _dst);
}
// xf_median_blur_config_tb.cpp
// 2020/03/08 by marsee
// xfopencv/HLS_Use_Model/Standalone_HLS_AXI_Example/xf_dilation_tb.cpp のコードを引用している
// https://github.com/Xilinx/xfopencv/blob/master/HLS_Use_Model/Standalone_HLS_AXI_Example/xf_dilation_tb.cpp
// xfopencv/examples/medianblur/xf_median_blur_tb.cpp のコードを引用している
// https://github.com/Xilinx/xfopencv/blob/master/examples/medianblur/xf_median_blur_tb.cpp
// 2022/01/10 : for Vitis Vision Library
#include "opencv2/opencv.hpp"
#include "opencv2/imgproc/imgproc.hpp"
#include "opencv2/highgui/highgui.hpp"
#include "opencv2/imgcodecs/imgcodecs.hpp"
#include "xf_median_blur.h"
#include "common/xf_axi.hpp"
#include "common/xf_sw_utils.hpp"
void median_blur_accel_axis(AXI_STREAM& _src, AXI_STREAM& _dst, int img_height, int img_width);
int main(int argc, char** argv)
{
if(argc != 2)
{
fprintf(stderr,"Invalid Number of Arguments!\nUsage:\n");
fprintf(stderr,"<Executable Name> <input image path> \n");
return -1;
}
cv::Mat out_img,ocv_ref;
cv::Mat in_img,in_img1,diff;
// reading in the color image
#if GRAY
in_img = cv::imread(argv[1], 0);
#else
in_img = cv::imread(argv[1], 1);
#endif
if (in_img.data == NULL)
{
fprintf(stderr,"Cannot open image at %s\n", argv[1]);
return 0;
}
// create memory for output images
/* reading the gray/color image */
#if GRAY
ocv_ref.create(in_img.rows,in_img.cols,CV_8UC1);
out_img.create(in_img.rows,in_img.cols,CV_8UC1);
diff.create(in_img.rows,in_img.cols,CV_8UC1);
in_img1.create(in_img.rows,in_img.cols,CV_8UC1);
#else
ocv_ref.create(in_img.rows,in_img.cols,CV_8UC3);
out_img.create(in_img.rows,in_img.cols,CV_8UC3);
diff.create(in_img.rows,in_img.cols,CV_8UC3);
in_img1.create(in_img.rows,in_img.cols,CV_8UC3);
#endif
int img_height = in_img.rows;
int img_width = in_img.cols;
///////////////// Opencv Reference ////////////////////////
cv::medianBlur(in_img,ocv_ref,WINDOW_SIZE);
cv::imwrite("out_ocv.jpg", ocv_ref);
AXI_STREAM _src,_dst;
xf::cv::cvMat2AXIvideoxf<NPxPC>(in_img, _src);
median_blur_accel_axis(_src, _dst, img_height, img_width);
xf::cv::AXIvideo2cvMatxf<NPxPC>(_dst, in_img1);
cv::imwrite("hls.jpg", in_img1);
////////////////// Compute Absolute Difference ////////////////////
cv::absdiff(ocv_ref, in_img1, diff);
float err_per;
xf::cv::analyzeDiff(diff,0,err_per);
cv::imwrite("diff_img.jpg",diff);
in_img.~Mat();
out_img.~Mat();
ocv_ref.~Mat();
in_img.~Mat();
in_img1.~Mat();
diff.~Mat();
if(err_per > 0.0f)
{
return 1;
}
return 0;
}
を設定した。-I/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Libraries/vision/L1/include -std=c++0x -I/usr/local/include
を設定した。-L/usr/local/lib -lopencv_core -lopencv_imgcodecs -lopencv_imgproc
を設定した。/media/masaaki/Ubuntu_Disk/Vitis_HLS/ZYBO_Z7_20/2021.2/xf_median_blur/test2.jpg
を設定した。-I/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Libraries/vision/L1/include -std=c++0x
を設定した。-I/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Libraries/vision/L1/include -std=c++0x
ERROR: [SYNCHK 200-61] /media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Libraries/vision/L1/include/common/xf_utility.hpp:66:
unsupported memory access on variable 'tmp_buf' which is (or contains) an array with unknown size at compile time.
だった。ERROR: [HLS 207-812] 'common/xf_common.hpp' file not found (xf_dilation/xf_dilation_config.h:22:10)
xf_dilation_accel.cpp
xf_dilation_config.h
xf_dilation_tb.cpp
xf_config_params.h
を設定した。-I/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Libraries/vision/L1/include -std=c++0x -I/usr/local/include
を設定した。-L/usr/local/lib -lopencv_core -lopencv_imgcodecs -lopencv_imgproc
を指定した。/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Libraries/vision/data/128x128.png
を設定した。-I/media/masaaki/Ubuntu_Disk/Xilinx_github/Vitis_Libraries/vision/L1/include -std=c++0x
1 ビッ ト CDC CDC-1 クリティカル 1 ビッ ト CDC パスが、 同期化されていないか、 または不明の CDC 回路を含みます。
だそうだ。CE 制御の CDC CDC-15 警告 ク ロ ッ ク イネーブルで制御された CDC。
## add_wave /apatb_DMA_pow2_top/m_axi_gmem_BUSER -into $wdata_group -radix hex
ERROR: [Wavedata 42-471] Note: Nothing was found for the following items: /apatb_DMA_pow2_top/m_axi_gmem_BUSER
ERROR: [Common 17-39] 'add_wave' failed due to earlier errors.
while executing
"add_wave /apatb_DMA_pow2_top/m_axi_gmem_BUSER -into $wdata_group -radix hex"
(file "DMA_pow2.tcl" line 103)
// ==============================================================
// Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2021.2 (64-bit)
// Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
// ==============================================================
`timescale 1ns/1ps
module DMA_pow2_control_s_axi
#(parameter
C_S_AXI_ADDR_WIDTH = 6,
C_S_AXI_DATA_WIDTH = 32
)(
input wire ACLK,
input wire ARESET,
input wire ACLK_EN,
input wire [C_S_AXI_ADDR_WIDTH-1:0] AWADDR,
input wire AWVALID,
output wire AWREADY,
input wire [C_S_AXI_DATA_WIDTH-1:0] WDATA,
input wire [C_S_AXI_DATA_WIDTH/8-1:0] WSTRB,
input wire WVALID,
output wire WREADY,
output wire [1:0] BRESP,
output wire BVALID,
input wire BREADY,
input wire [C_S_AXI_ADDR_WIDTH-1:0] ARADDR,
input wire ARVALID,
output wire ARREADY,
output wire [C_S_AXI_DATA_WIDTH-1:0] RDATA,
output wire [1:0] RRESP,
output wire RVALID,
input wire RREADY,
output wire interrupt,
input wire clk,
input wire rst,
output wire ap_start,
input wire ap_done,
input wire ap_ready,
input wire ap_idle,
input wire [31:0] ap_return,
output wire [63:0] in_r,
output wire [63:0] out_r,
input wire [0:0] ap_local_deadlock
);
//------------------------Address Info-------------------
// 0x00 : Control signals
// bit 0 - ap_start (Read/Write/COH)
// bit 1 - ap_done (Read/COR)
// bit 2 - ap_idle (Read)
// bit 3 - ap_ready (Read/COR)
// bit 7 - auto_restart (Read/Write)
// others - reserved
// 0x04 : Global Interrupt Enable Register
// bit 0 - Global Interrupt Enable (Read/Write)
// others - reserved
// 0x08 : IP Interrupt Enable Register (Read/Write)
// bit 0 - enable ap_done interrupt (Read/Write)
// bit 1 - enable ap_ready interrupt (Read/Write)
// bit 5 - enable ap_local_deadlock interrupt (Read/Write)
// others - reserved
// 0x0c : IP Interrupt Status Register (Read/TOW)
// bit 0 - ap_done (COR/TOW)
// bit 1 - ap_ready (COR/TOW)
// bit 5 - ap_local_deadlock (COR/TOW)
// others - reserved
// 0x10 : Data signal of ap_return
// bit 31~0 - ap_return[31:0] (Read)
// 0x18 : Data signal of in_r
// bit 31~0 - in_r[31:0] (Read/Write)
// 0x1c : Data signal of in_r
// bit 31~0 - in_r[63:32] (Read/Write)
// 0x20 : reserved
// 0x24 : Data signal of out_r
// bit 31~0 - out_r[31:0] (Read/Write)
// 0x28 : Data signal of out_r
// bit 31~0 - out_r[63:32] (Read/Write)
// 0x2c : reserved
// (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
//------------------------Parameter----------------------
localparam
ADDR_AP_CTRL = 6'h00,
ADDR_GIE = 6'h04,
ADDR_IER = 6'h08,
ADDR_ISR = 6'h0c,
ADDR_AP_RETURN_0 = 6'h10,
ADDR_IN_R_DATA_0 = 6'h18,
ADDR_IN_R_DATA_1 = 6'h1c,
ADDR_IN_R_CTRL = 6'h20,
ADDR_OUT_R_DATA_0 = 6'h24,
ADDR_OUT_R_DATA_1 = 6'h28,
ADDR_OUT_R_CTRL = 6'h2c,
WRIDLE = 2'd0,
WRDATA = 2'd1,
WRRESP = 2'd2,
WRRESET = 2'd3,
RDIDLE = 2'd0,
RDDATA = 2'd1,
RDRESET = 2'd2,
ADDR_BITS = 6;
//------------------------Local signal-------------------
reg [1:0] wstate = WRRESET;
reg [1:0] wnext;
reg [ADDR_BITS-1:0] waddr;
wire [C_S_AXI_DATA_WIDTH-1:0] wmask;
wire aw_hs;
wire w_hs;
reg [1:0] rstate = RDRESET;
reg [1:0] rnext;
reg [C_S_AXI_DATA_WIDTH-1:0] rdata;
wire ar_hs;
wire [ADDR_BITS-1:0] raddr;
// internal registers
reg int_ap_idle;
reg int_ap_ready = 1'b0;
reg int_ap_done = 1'b0;
wire ap_done_get;
reg ap_done_ext;
reg int_ap_start = 1'b0;
wire ap_start_set;
reg ap_start_mask;
reg int_auto_restart = 1'b0;
wire auto_restart_set;
reg int_gie = 1'b0;
reg [5:0] int_ier = 6'b0;
wire ier_toggle;
reg ier_mask;
reg [5:0] int_isr = 6'b0;
wire isr_toggle;
reg isr_mask;
reg [31:0] int_ap_return;
reg [63:0] int_in_r = 'b0;
reg [63:0] int_out_r = 'b0;
//------------------------Instantiation------------------
//------------------------AXI write fsm------------------
assign AWREADY = (wstate == WRIDLE);
assign WREADY = (wstate == WRDATA);
assign BRESP = 2'b00; // OKAY
assign BVALID = (wstate == WRRESP);
assign wmask = { {8{WSTRB[3]}}, {8{WSTRB[2]}}, {8{WSTRB[1]}}, {8{WSTRB[0]}} };
assign aw_hs = AWVALID & AWREADY;
assign w_hs = WVALID & WREADY;
// wstate
always @(posedge ACLK) begin
if (ARESET)
wstate <= WRRESET;
else if (ACLK_EN)
wstate <= wnext;
end
// wnext
always @(*) begin
case (wstate)
WRIDLE:
if (AWVALID)
wnext = WRDATA;
else
wnext = WRIDLE;
WRDATA:
if (WVALID)
wnext = WRRESP;
else
wnext = WRDATA;
WRRESP:
if (BREADY)
wnext = WRIDLE;
else
wnext = WRRESP;
default:
wnext = WRIDLE;
endcase
end
// waddr
always @(posedge ACLK) begin
if (ACLK_EN) begin
if (aw_hs)
waddr <= AWADDR[ADDR_BITS-1:0];
end
end
//------------------------AXI read fsm-------------------
assign ARREADY = (rstate == RDIDLE);
assign RDATA = rdata;
assign RRESP = 2'b00; // OKAY
assign RVALID = (rstate == RDDATA);
assign ar_hs = ARVALID & ARREADY;
assign raddr = ARADDR[ADDR_BITS-1:0];
// rstate
always @(posedge ACLK) begin
if (ARESET)
rstate <= RDRESET;
else if (ACLK_EN)
rstate <= rnext;
end
// rnext
always @(*) begin
case (rstate)
RDIDLE:
if (ARVALID)
rnext = RDDATA;
else
rnext = RDIDLE;
RDDATA:
if (RREADY & RVALID)
rnext = RDIDLE;
else
rnext = RDDATA;
default:
rnext = RDIDLE;
endcase
end
// rdata
always @(posedge ACLK) begin
if (ACLK_EN) begin
if (ar_hs) begin
rdata <= 'b0;
case (raddr)
ADDR_AP_CTRL: begin
rdata[0] <= int_ap_start;
rdata[1] <= int_ap_done;
rdata[2] <= int_ap_idle;
rdata[3] <= int_ap_ready;
rdata[7] <= int_auto_restart;
end
ADDR_GIE: begin
rdata <= int_gie;
end
ADDR_IER: begin
rdata <= int_ier;
end
ADDR_ISR: begin
rdata <= int_isr;
end
ADDR_AP_RETURN_0: begin
rdata <= int_ap_return[31:0];
end
ADDR_IN_R_DATA_0: begin
rdata <= int_in_r[31:0];
end
ADDR_IN_R_DATA_1: begin
rdata <= int_in_r[63:32];
end
ADDR_OUT_R_DATA_0: begin
rdata <= int_out_r[31:0];
end
ADDR_OUT_R_DATA_1: begin
rdata <= int_out_r[63:32];
end
endcase
end
end
end
//------------------------Register logic-----------------
assign interrupt = int_gie & (|int_isr);
assign ap_start = int_ap_start;
assign ap_start_set = w_hs && waddr == ADDR_AP_CTRL && WSTRB[0] && WDATA[0];
assign ap_done_get = ar_hs && raddr == ADDR_AP_CTRL && int_ap_done;
assign auto_restart_set = w_hs && waddr == ADDR_AP_CTRL && WSTRB[0];
assign isr_toggle = w_hs && waddr == ADDR_ISR && WSTRB[0];
assign in_r = int_in_r;
assign out_r = int_out_r;
// ap_start_mask
always @(posedge clk) begin
if (rst)
ap_start_mask <= 1'b0;
else
ap_start_mask <= ap_start_set;
end
// int_ap_start
always @(posedge clk) begin
if (rst)
int_ap_start <= 1'b0;
else if (ap_start_set == 1'b1 && ap_start_mask == 1'b0)
int_ap_start <= 1'b1;
else if (ap_ready)
int_ap_start <= int_auto_restart; // clear on handshake/auto restart
end
// ap_done_ext
always @(posedge clk) begin
if (rst)
ap_done_ext <= 1'b0;
else
ap_done_ext <= ap_done_get;
end
// int_ap_done
always @(posedge clk) begin
if (rst)
int_ap_done <= 1'b0;
else if (ap_done)
int_ap_done <= 1'b1;
else if (ap_done_get == 1'b0 && ap_done_ext == 1'b1)
int_ap_done <= 1'b0; // clear on read
end
// int_ap_idle
always @(posedge clk) begin
if (rst)
int_ap_idle <= 1'b0;
else
int_ap_idle <= ap_idle;
end
// int_ap_ready
always @(posedge clk) begin
if (rst)
int_ap_ready <= 1'b0;
else
int_ap_ready <= ap_ready;
end
// int_auto_restart
always @(posedge clk) begin
if (rst)
int_auto_restart <= 1'b0;
else if (auto_restart_set == 1'b1)
int_auto_restart <= WDATA[7];
end
// int_gie
always @(posedge clk) begin
if (rst)
int_gie <= 1'b0;
else if (w_hs && waddr == ADDR_GIE && WSTRB[0])
int_gie <= WDATA[0];
end
// int_ier
always @(posedge clk) begin
if (rst)
int_ier <= 'b0;
else if (w_hs && waddr == ADDR_IER && WSTRB[0])
int_ier <= WDATA[5:0];
else if (w_hs && waddr == ADDR_IER && WSTRB[0])
int_ier <= WDATA[5:0];
end
// isr_mask
always @(posedge clk) begin
if (rst)
isr_mask <= 1'b0;
else
isr_mask <= isr_toggle;
end
// int_isr[0]
always @(posedge clk) begin
if (rst)
int_isr[0] <= 1'b0;
else if (int_ier[0] & ap_done)
int_isr[0] <= 1'b1;
else if (isr_toggle == 1'b1 && isr_mask == 1'b0)
int_isr[0] <= int_isr[0] ^ WDATA[0]; // toggle on write
end
// int_isr[1]
always @(posedge clk) begin
if (rst)
int_isr[1] <= 1'b0;
else if (int_ier[1] & ap_ready)
int_isr[1] <= 1'b1;
else if (isr_toggle == 1'b1 && isr_mask == 1'b0)
int_isr[1] <= int_isr[1] ^ WDATA[1]; // toggle on write
end
// int_isr[5]
always @(posedge clk) begin
if (rst)
int_isr[5] <= 1'b0;
else if (int_ier[5] & ap_local_deadlock)
int_isr[5] <= 1'b1;
else if (isr_toggle == 1'b1 && isr_mask == 1'b0)
int_isr[5] <= int_isr[5] ^ WDATA[5]; // toggle on write
end
// int_ap_return
always @(posedge clk) begin
if (rst)
int_ap_return <= 0;
else if (ap_done)
int_ap_return <= ap_return;
end
// int_in_r[31:0]
always @(posedge clk) begin
if (rst)
int_in_r[31:0] <= 0;
else if (w_hs && waddr == ADDR_IN_R_DATA_0)
int_in_r[31:0] <= (WDATA[31:0] & wmask) | (int_in_r[31:0] & ~wmask);
end
// int_in_r[63:32]
always @(posedge clk) begin
if (rst)
int_in_r[63:32] <= 0;
else if (w_hs && waddr == ADDR_IN_R_DATA_1)
int_in_r[63:32] <= (WDATA[31:0] & wmask) | (int_in_r[63:32] & ~wmask);
end
// int_out_r[31:0]
always @(posedge clk) begin
if (rst)
int_out_r[31:0] <= 0;
else if (w_hs && waddr == ADDR_OUT_R_DATA_0)
int_out_r[31:0] <= (WDATA[31:0] & wmask) | (int_out_r[31:0] & ~wmask);
end
// int_out_r[63:32]
always @(posedge clk) begin
if (rst)
int_out_r[63:32] <= 0;
else if (w_hs && waddr == ADDR_OUT_R_DATA_1)
int_out_r[63:32] <= (WDATA[31:0] & wmask) | (int_out_r[63:32] & ~wmask);
end
//------------------------Memory logic-------------------
endmodule
Vitis HLSでIPを生成しようとするとエラーが発生した。中国語だが、以下の記事と同じ現象。2022年になったから発生するということかな。
— ひがし (@phys_higashi) January 2, 2022
システム時刻を戻すとうまくいくらしい。https://t.co/CSr9YkHsg5
ERROR: '2201021549' is an invalid argument. Please specify an integer value.
while executing
"rdi::set_property core_revision 2201021549 {component component_1}"
invoked from within
"set_property core_revision $Revision $core"
(file "run_ippack.tcl" line 1109)
set Revision "2201021811"（年月日時分）
set Revision "2001012126"
-clock
デフォルトでは、AXI4-Lite インターフェイス クロックはシステム クロックと同じです。このオプションを使用すると、AXI4-Lite インターフェイスに別のクロックを指定できます。-bundle オプションを使用して複数の最上位関数引数を 1 つの AXI4-Lite インターフェイスにまとめている場合は、-clock オプションはバンドル メンバーの 1 つにのみ指定します。
// DMA_pow2_defclk.cpp
// 2022/01/02 by marsee
//
#include <stdint.h>
int DMA_pow2(int32_t *in, int32_t *out){
#pragma HLS INTERFACE mode=s_axilite bundle=control clock=axi4l_clk port=return
#pragma HLS INTERFACE mode=s_axilite bundle=control port=out
#pragma HLS INTERFACE mode=s_axilite bundle=control port=in
#pragma HLS INTERFACE mode=m_axi depth=10 port=out offset=slave
#pragma HLS INTERFACE mode=m_axi depth=10 port=in offset=slave
for(int i=0; i<10; i++){
out[i] = in[i] * in[i];
}
return(0);
}
// DMA_pow2_defclk_tb.cpp
// 2021/01/02 by marsee
//
#include <iostream>
#include <stdint.h>
int DMA_pow2(int32_t *in, int32_t *out);
int main(){
int32_t data[10] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9};
int32_t result[10];
DMA_pow2(data, result);
for(int i=0; i<10; i++){
std::cout << "data[" << i << "]= " << data[i] <<
", result[" << i << "] = " <<
result[i] << std::endl;
}
}
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