Design Summary
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Number of errors: 0
Number of warnings: 11
Logic Utilization:
Number of Slice Flip Flops: 2,137 out of 9,312 22%
Number of 4 input LUTs: 3,444 out of 9,312 36%
Logic Distribution:
Number of occupied Slices: 2,455 out of 4,656 52%
Number of Slices containing only related logic: 2,455 out of 2,455 100%
Number of Slices containing unrelated logic: 0 out of 2,455 0%
*See NOTES below for an explanation of the effects of unrelated logic.
Total Number of 4 input LUTs: 3,549 out of 9,312 38%
Number used as logic: 2,811
Number used as a route-thru: 105
Number used for Dual Port RAMs: 632
(Two LUTs used per Dual Port RAM)
Number used as Shift registers: 1
Number of bonded IOBs: 64 out of 232 27%
IOB Flip Flops: 18
Number of IDDR2s used: 16
Number of DDR_ALIGNMENT = NONE 16
Number of DDR_ALIGNMENT = C0 0
Number of DDR_ALIGNMENT = C1 0
Number of ODDR2s used: 38
Number of DDR_ALIGNMENT = NONE 38
Number of DDR_ALIGNMENT = C0 0
Number of DDR_ALIGNMENT = C1 0
Number of RAMB16s: 7 out of 20 35%
Number of BUFGMUXs: 5 out of 24 20%
Number of DCMs: 2 out of 4 50%
Number of MULT18X18SIOs: 3 out of 20 15%
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17 | 18 | 19 | 20 | 21 | 22 | 23 |
24 | 25 | 26 | 27 | 28 | 29 | 30 |