-- CharDispCtrlerTest.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
entity CharDispCtrlerTest is
port(
clk : in std_logic;
reset : in std_logic;
dvi_xclk_p : out std_logic;
dvi_xclk_n : out std_logic;
dvi_reset_b : out std_logic;
dvi_hsync : out std_logic;
dvi_vsync : out std_logic;
dvi_de : out std_logic;
dvi_d : out std_logic_vector(11 downto 0)
);
end CharDispCtrlerTest;
ODDR_dvi_xclk_p : ODDR
port map(
Q => dvi_xclk_p,
C => clkdv,
CE => '1',
D1 => '1',
D2 => '0',
R => reset,
S => '0'
);
ODDR_dvi_xclk_n : ODDR generic map(
DDR_CLK_EDGE => "OPPOSITE_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE"
INIT => '1', -- Initial value for Q port (’1’ or ’0’)
SRTYPE => "SYNC") -- Reset Type ("ASYNC" or "SYNC")
port map(
Q => dvi_xclk_n,
C => clkdv,
CE => '1',
D1 => '0',
D2 => '1',
R => reset,
S => '0'
);
WARNING:HDLCompiler:89 - "C:/HDL/FndISEWork/Virtex5_VLX110T/CharDispCtrler/CharDispCtrlerTest/CharDispCtrlerTest_synth/../CharDispCtrlerTest.vhd" Line 191:
remains a black-box since it has no binding entity.
-- CharDispCtrlerTest.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
library unisim;
use unisim.vcomponents.all;
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