-- implement slave model software accessible register(s) read mux
SLAVE_REG_READ_PROC : process( slv_reg_read_sel, SCCBbusy ) is
begin
-- スレーブIPのReadは、最下位ビットにSCCBbusy が割り当てられる。
case slv_reg_read_sel is
when "1" =>
slv_ip2bus_data(0 to C_SLV_DWIDTH-2) <= (others => '0');
slv_ip2bus_data(C_SLV_DWIDTH-1) <= SCCBbusy;
when others => slv_ip2bus_data <= (others => '0');
end case;
end process SLAVE_REG_READ_PROC;
------------------------------------------
-- Example code to drive IP to Bus signals
------------------------------------------
IP2Bus_Data <= slv_ip2bus_data when slv_read_ack = '1' else
(others => '0');
IP2Bus_WrAck <= slv_write_ack;
IP2Bus_RdAck <= slv_read_ack;
IP2Bus_Error <= '0';
-- SCCB_Reg_Controller.vhd を接続
-- ad_enable を生成する
process( Bus2IP_Clk ) begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Resetn = '0' then
ad_enable <= '0';
else
if slv_reg_write_sel="01" then
ad_enable <= '1';
else
ad_enable <= '0';
end if;
end if;
end if;
end process;
Bus2IP_Reset <= not Bus2IP_Resetn;
addr_data <= slv_reg0(16 to 31); -- 下位16ビット
SCCB_Reg_Controller_inst : SCCB_Reg_Controller port map(
clkin => Bus2IP_Clk,
reset => Bus2IP_Reset,
addr_data => addr_data,
ad_enable => ad_enable,
SCCBbusy => SCCBbusy,
SCL => SCL,
SDA => SDA
);
entity user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_SLV_DWIDTH : integer := 32;
C_NUM_REG : integer := 1
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
SCL : out std_logic; -- SCCBのクロック
SDA : out std_logic; -- SCCBのデータ
-- ADD USER PORTS ABOVE THIS LINE ------------------
entity sccb_controller is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_SPLB_AWIDTH : integer := 32;
C_SPLB_DWIDTH : integer := 128;
C_SPLB_NUM_MASTERS : integer := 8;
C_SPLB_MID_WIDTH : integer := 3;
C_SPLB_NATIVE_DWIDTH : integer := 32;
C_SPLB_P2P : integer := 0;
C_SPLB_SUPPORT_BURSTS : integer := 0;
C_SPLB_SMALLEST_MASTER : integer := 32;
C_SPLB_CLK_PERIOD_PS : integer := 10000;
C_INCLUDE_DPHASE_TIMER : integer := 1;
C_FAMILY : string := "virtex6"
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
-- ADD USER PORTS ABOVE THIS LINE ------------------
SCL : out std_logic; -- SCCBのクロック
SDA : out std_logic; -- SCCBのデータ
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
USER_LOGIC_I : entity sccb_controller_v1_00_a.user_logic
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
--USER generics mapped here
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_SLV_DWIDTH => USER_SLV_DWIDTH,
C_NUM_REG => USER_NUM_REG
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
--USER ports mapped here
SCL => SCL,
SDA => SDA
-- MAP USER PORTS ABOVE THIS LINE ------------------
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Reset => ipif_Bus2IP_Reset,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error
);
##############################################################################
## Filename: H:/HDL/FndtnISEWork/Spartan3A_starter_kit/CamDisp_EDK_OV7670/system/pcores/sccb_controller_v1_00_a/data/sccb_controller_v2_1_0.pao
## Description: Peripheral Analysis Order
## Date: Sun Aug 21 18:10:38 2011 (by Create and Import Peripheral Wizard)
##############################################################################
lib proc_common_v3_00_a all
lib plbv46_slave_single_v1_01_a all
lib sccb_controller_v1_00_a user_logic vhdl
lib sccb_controller_v1_00_a sccb_controller vhdl
lib sccb_controller_v1_00_a SCCB_reg_values_ROM.vhd vhdl
lib sccb_controller_v1_00_a freqdiv.vhd vhdl
lib sccb_controller_v1_00_a One_Transaction_SCCB.vhd vhdl
lib sccb_controller_v1_00_a SCCB_Reg_Controller.vhd vhdl
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