//-----------------------------------------------------------------------------
// system_stub.v
//-----------------------------------------------------------------------------
module system_stub
(
RESET,
Led,
CLK,
axi_uartlite_0_RX_pin,
axi_uartlite_0_TX_pin
);
input RESET;
output [0:7] Led;
input CLK;
input axi_uartlite_0_RX_pin;
output axi_uartlite_0_TX_pin;
(* BOX_TYPE = "user_black_box" *)
system
system_i (
.RESET ( RESET ),
.Led ( Led ),
.CLK ( CLK ),
.axi_uartlite_0_RX_pin ( axi_uartlite_0_RX_pin ),
.axi_uartlite_0_TX_pin ( axi_uartlite_0_TX_pin )
);
endmodule
NET "CLK" LOC = "L15" | IOSTANDARD = LVCMOS33; # Bank = 1, Pin name = IO_L42P_GCLK7_M1UDM, Type = GCLK, Sch name = GCLK
NET "RESET" LOC = "T15" | IOSTANDARD = LVCMOS33; # Bank = 2, Pin name = IO_L1N_M0_CMPMISO_2, Sch name = M0/RESET
NET "Led<0>" LOC = "U18" | IOSTANDARD = LVCMOS33; # Bank = 1, Pin name = IO_L52N_M1DQ15, Sch name = LD0
NET "Led<1>" LOC = "M14" | IOSTANDARD = LVCMOS33; # Bank = 1, Pin name = IO_L53P, Sch name = LD1
NET "Led<2>" LOC = "N14" | IOSTANDARD = LVCMOS33; # Bank = 1, Pin name = IO_L53N_VREF, Sch name = LD2
NET "Led<3>" LOC = "L14" | IOSTANDARD = LVCMOS33; # Bank = 1, Pin name = IO_L61P, Sch name = LD3
NET "Led<4>" LOC = "M13" | IOSTANDARD = LVCMOS33; # Bank = 1, Pin name = IO_L61N, Sch name = LD4
NET "Led<5>" LOC = "D4" | IOSTANDARD = LVCMOS33; # Bank = 0, Pin name = IO_L1P_HSWAPEN_0, Sch name = HSWAP/LD5
NET "Led<6>" LOC = "P16" | IOSTANDARD = LVCMOS33; # Bank = 1, Pin name = IO_L74N_DOUT_BUSY_1, Sch name = LD6
NET "Led<7>" LOC = "N12" | IOSTANDARD = LVCMOS33; # Bank = 2, Pin name = IO_L13P_M1_2, Sch name = M1/LD7
NET "axi_uartlite_0_RX_pin" IOSTANDARD = LVCMOS33;
NET "axi_uartlite_0_RX_pin" LOC = A16;
NET "axi_uartlite_0_TX_pin" IOSTANDARD = LVCMOS33;
NET "axi_uartlite_0_TX_pin" LOC = B16;
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