-------------------------------------------------------------------------------
--
-- AXI Master
--
-- VHDL-Standard: VHDL'93
----------------------------------------------------------------------------
--
-- Structure:
-- mt9d111_inf_axi_master
--
----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
--library unisim;
--use unisim.vcomponents.all;
entity mt9d111_inf_axi_master is
generic(
C_M_AXI_SUPPORTS_THREADS : integer := 0;
C_M_AXI_THREAD_ID_WIDTH : integer := 1;
C_M_AXI_ADDR_WIDTH : integer := 32;
C_M_AXI_DATA_WIDTH : integer := 64;
C_INTERCONNECT_M_AXI_WRITE_ISSUING : integer := 8;
C_INTERCONNECT_M_AXI_READ_ISSUING : integer := 8;
C_M_AXI_SUPPORTS_READ : integer := 0;
C_M_AXI_SUPPORTS_WRITE : integer := 1;
C_M_AXI_SUPPORTS_USER_SIGNALS : integer := 0;
C_M_AXI_AWUSER_WIDTH : integer := 1;
C_M_AXI_ARUSER_WIDTH : integer := 1;
C_M_AXI_WUSER_WIDTH : integer := 1;
C_M_AXI_RUSER_WIDTH : integer := 1;
C_M_AXI_BUSER_WIDTH : integer := 1;
C_M_AXI_SUPPORTS_NARROW_BURST : integer := 0;
C_M_AXI_TARGET : std_logic_vector(31 downto 0) := x"00000000";
C_M_AXI_BURST_LEN : integer := 16;
C_OFFSET_WIDTH : integer := 9;
C_DISPLAY_START_ADDRESS : std_logic_vector(31 downto 0) := x"10000000";
C_UPSIDE_DOWN : integer := 0 -- 1 = 上下反転、0 = 正常
);
port(
-- System Signals
ACLK : in std_logic;
ARESETN : in std_logic;
-- Master Interface Write Address
M_AXI_AWID : out std_logic_vector(C_M_AXI_THREAD_ID_WIDTH-1 downto 0);
M_AXI_AWADDR : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
M_AXI_AWLEN : out std_logic_vector(8-1 downto 0);
M_AXI_AWSIZE : out std_logic_vector(3-1 downto 0);
M_AXI_AWBURST : out std_logic_vector(2-1 downto 0);
M_AXI_AWLOCK : out std_logic;
M_AXI_AWCACHE : out std_logic_vector(4-1 downto 0);
M_AXI_AWPROT : out std_logic_vector(3-1 downto 0);
-- AXI3 M_AXI_AWREGION:out std_logic_vector(4-1 downto 0);
M_AXI_AWQOS : out std_logic_vector(4-1 downto 0);
M_AXI_AWUSER : out std_logic_vector(C_M_AXI_AWUSER_WIDTH-1 downto 0);
M_AXI_AWVALID : out std_logic;
M_AXI_AWREADY : in std_logic;
-- Master Interface Write Data
-- AXI3 M_AXI_WID(C_M_AXI_THREAD_ID_WIDTH-1 downto 0);
M_AXI_WDATA : out std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
M_AXI_WSTRB : out std_logic_vector(C_M_AXI_DATA_WIDTH/8-1 downto 0);
M_AXI_WLAST : out std_logic;
M_AXI_WUSER : out std_logic_vector(C_M_AXI_WUSER_WIDTH-1 downto 0);
M_AXI_WVALID : out std_logic;
M_AXI_WREADY : in std_logic;
-- Master Interface Write Response
M_AXI_BID : in std_logic_vector(C_M_AXI_THREAD_ID_WIDTH-1 downto 0);
M_AXI_BRESP : in std_logic_vector(2-1 downto 0);
M_AXI_BUSER : in std_logic_vector(C_M_AXI_BUSER_WIDTH-1 downto 0);
M_AXI_BVALID : in std_logic;
M_AXI_BREADY : out std_logic;
-- Master Interface Read Address
M_AXI_ARID : out std_logic_vector(C_M_AXI_THREAD_ID_WIDTH-1 downto 0);
M_AXI_ARADDR : out std_logic_vector(C_M_AXI_ADDR_WIDTH-1 downto 0);
M_AXI_ARLEN : out std_logic_vector(8-1 downto 0);
M_AXI_ARSIZE : out std_logic_vector(3-1 downto 0);
M_AXI_ARBURST : out std_logic_vector(2-1 downto 0);
M_AXI_ARLOCK : out std_logic_vector(2-1 downto 0);
M_AXI_ARCACHE : out std_logic_vector(4-1 downto 0);
M_AXI_ARPROT : out std_logic_vector(3-1 downto 0);
-- AXI3 M_AXI_ARREGION:out std_logic_vector(4-1 downto 0);
M_AXI_ARQOS : out std_logic_vector(4-1 downto 0);
M_AXI_ARUSER : out std_logic_vector(C_M_AXI_ARUSER_WIDTH-1 downto 0);
M_AXI_ARVALID : out std_logic;
M_AXI_ARREADY : in std_logic;
-- Master Interface Read Data
M_AXI_RID : in std_logic_vector(C_M_AXI_THREAD_ID_WIDTH-1 downto 0);
M_AXI_RDATA : in std_logic_vector(C_M_AXI_DATA_WIDTH-1 downto 0);
M_AXI_RRESP : in std_logic_vector(2-1 downto 0);
M_AXI_RLAST : in std_logic;
M_AXI_RUSER : in std_logic_vector(C_M_AXI_RUSER_WIDTH-1 downto 0);
M_AXI_RVALID : in std_logic;
M_AXI_RREADY : out std_logic;
init_done : in std_logic;
wr_error : out std_logic; -- AXI4 Write 時のエラー（M_AXI_BRESP/=RESP_OKAY）
-- MT9D111 Camera Interface
pclk_from_pll : in std_logic; -- PLLからMT9D111のxck に出力するクロック
pclk : in std_logic; -- MT9D111からのピクセルクロック入力
xck : out std_logic; -- MT9D111へのピクセルクロック出力
href : in std_logic;
vsync : in std_logic;
cam_data : in std_logic_vector(7 downto 0);
standby : out std_logic; -- STANDBY出力（ディスエーブル、0固定）
pfifo_overflow : out std_logic; -- pfifo overflow
pfifo_underflow : out std_logic -- pfifo underflow
);
end mt9d111_inf_axi_master;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of mt9d111_inf_axi_master is
constant RESP_OKAY : std_logic_vector := "00";
constant RESP_EXOKAY : std_logic_vector := "01";
constant RESP_SLVERR : std_logic_vector := "10";
constant RESP_DECERR : std_logic_vector := "11";
constant DDR3_START_ADDR : std_logic_vector := x"10000000";
constant ROW_ALL_PIXELS : integer := 640;
constant COULMN_ALL_PIXELS : integer := 480;
constant SVGA_ADDR_LIMIT : integer := ROW_ALL_PIXELS*COULMN_ALL_PIXELS*4; -- SVGAのアドレスリミット（横ピクセル数 * 縦ピクセル数 * 1ピクセルを表すバイト数）
signal reset_1d, reset_2d, reset : std_logic;
type wr_main_transaction_state is (idle_wr_main, write_state);
signal wr_main_cs, wr_main_1d : wr_main_transaction_state;
type write_transaction_state is (idle_wr, awvalid_assert, data_write_hold, bready_assert, wr_tran_end);
signal wrt_cs : write_transaction_state;
type write_wvalid_state is (idle_wvalid, wvalid_assert, wvalid_hold);
signal wrt_wv_cs : write_wvalid_state;
signal awvalid, wvalid, bready : std_logic;
signal awlen, write_count : std_logic_vector(7 downto 0);
signal wlast : std_logic;
signal preset_1d, preset_2d, preset : std_logic;
signal pfifo_empty : std_logic;
signal pfifo_almost_empty : std_logic;
signal pfifo_rd_data_count : std_logic_vector(9 downto 0);
signal pfifo_rd_dcount_dec : unsigned(9 downto 0);
signal pfifo_rd_en : std_logic;
component mt9d111_cam_cont generic (
DISPLAY_START_ADDRESS : std_logic_vector(31 downto 0) := x"10000000";
UPSIDE_DOWN : integer := 0
);
port(
aclk : in std_logic;
areset : in std_logic;
pclk : in std_logic;
preset : in std_logic;
pclk_from_pll : in std_logic;
xclk : out std_logic;
line_valid : in std_logic;
frame_valid : in std_logic;
cam_data : in std_logic_vector(7 downto 0);
standby : out std_logic;
paddr : out std_logic_vector(31 downto 0);
pfifo_rd_en : in std_logic;
pfifo_dout : out std_logic_vector(63 downto 0);
pfifo_empty : out std_logic;
pfifo_almost_empty : out std_logic;
pfifo_rd_data_count : out std_logic_vector(9 downto 0);
pfifo_overflow : out std_logic;
pfifo_underflow : out std_logic
);
end component;
begin
-- ARESETN をACLK で同期化
process (ACLK) begin
if ACLK'event and ACLK='1' then
reset_1d <= not ARESETN or not init_done;
reset_2d <= reset_1d;
end if;
end process;
reset <= reset_2d;
-- ARESETN をpclk で同期化
process(pclk) begin
if pclk'event and pclk='1' then
preset_1d <= not ARESETN or not init_done;
preset_2d <= preset_1d;
end if;
end process;
preset <= preset_2d;
-- Write Transaction State Machine
-- ピクセルデータが存在する時(pfifo_empty=0)の時に、 Writeを行う。Readは無し
process(ACLK) begin
if ACLK'event and ACLK='1' then
if reset='1' then
wr_main_cs <= idle_wr_main;
else
case (wr_main_cs) is
when idle_wr_main =>
if pfifo_rd_data_count/=std_logic_vector(to_unsigned(0, pfifo_rd_data_count'length)) then
wr_main_cs <= write_state;
end if;
when write_state =>
if wrt_cs = wr_tran_end then -- pfifo のピクセルデータをAXI4バス経由で転送終了
wr_main_cs <= idle_wr_main;
end if;
end case;
end if;
end if;
end process;
pfifo_rd_en <= M_AXI_WREADY and wvalid;
mt9d111_cam_cont_i : mt9d111_cam_cont generic map(
DISPLAY_START_ADDRESS => C_DISPLAY_START_ADDRESS,
UPSIDE_DOWN => C_UPSIDE_DOWN
)port map(
aclk => ACLK,
areset => reset,
pclk => pclk,
preset => preset,
pclk_from_pll => pclk_from_pll,
xclk => xck,
line_valid => href,
frame_valid => vsync,
cam_data => cam_data,
standby => standby,
paddr => M_AXI_AWADDR,
pfifo_rd_en => pfifo_rd_en,
pfifo_dout => M_AXI_WDATA,
pfifo_empty => pfifo_empty,
pfifo_almost_empty => pfifo_almost_empty,
pfifo_rd_data_count => pfifo_rd_data_count,
pfifo_overflow => pfifo_overflow,
pfifo_underflow => pfifo_underflow
);
-- Write
M_AXI_AWID <= "0";
M_AXI_AWSIZE <= "011"; -- 8 bytes fixed
M_AXI_AWBURST <= "01"; -- INCR
M_AXI_AWLOCK <= '0'; -- Normal Access
M_AXI_AWCACHE <= "0010"; -- Normal Non-cacheable Non-bufferable
-- M_AXI_AWCACHE <= "0011"; -- Normal Non-cacheable Bufferable, Zynq-7020ではBRESPが10でSLVERRになってしまい設定してはならない。
M_AXI_AWPROT <= "000"; -- Data access, Secure access, Unprivileged access
M_AXI_AWQOS <= "0000"; -- default
M_AXI_AWUSER <= "0";
M_AXI_WSTRB <= (others => '1');
M_AXI_WUSER <= "0";
M_AXI_AWLEN <= awlen;
-- AXI4バス Write Transaction State Machine
process(ACLK) begin
if ACLK'event and ACLK='1' then
if reset='1' then
wrt_cs <= idle_wr;
awvalid <= '0';
bready <= '0';
else
case(wrt_cs) is
when idle_wr =>
if wr_main_cs = write_state then
wrt_cs <= awvalid_assert;
awvalid <= '1';
end if;
when awvalid_assert =>
if M_AXI_AWREADY='1' then
if wrt_wv_cs=wvalid_hold or (wrt_wv_cs=wvalid_assert and unsigned(write_count)=0 and M_AXI_WREADY='1') then
wrt_cs <= bready_assert;
bready <= '1';
else
wrt_cs <= data_write_hold;
end if;
awvalid <= '0';
end if;
when data_write_hold =>
if wrt_wv_cs=wvalid_hold or (wrt_wv_cs=wvalid_assert and unsigned(write_count)=0 and M_AXI_WREADY='1') then
wrt_cs <= bready_assert;
bready <= '1';
end if;
when bready_assert =>
if M_AXI_BVALID='1' then
wrt_cs <= wr_tran_end;
bready <= '0';
end if;
when wr_tran_end =>
wrt_cs <= idle_wr;
end case;
end if;
end if;
end process;
-- AXI4 バス Write Transaction WVALID State Machine
process(ACLK) begin
if ACLK'event and ACLK='1' then
if reset='1' then
wrt_wv_cs <= idle_wvalid;
wvalid <= '0';
else
case(wrt_wv_cs) is
when idle_wvalid =>
if wrt_cs=awvalid_assert then
wrt_wv_cs <= wvalid_assert;
wvalid <= '1';
end if;
when wvalid_assert =>
if unsigned(write_count)=0 and M_AXI_WREADY='1' then -- 終了
wrt_wv_cs <= wvalid_hold;
wvalid <= '0';
end if;
when wvalid_hold =>
if wrt_cs=bready_assert then
wrt_wv_cs <= idle_wvalid;
end if;
end case;
end if;
end if;
end process;
M_AXI_AWVALID <= awvalid;
M_AXI_WVALID <= wvalid;
M_AXI_BREADY <= bready;
-- write_count の処理
pfifo_rd_dcount_dec <= unsigned(pfifo_rd_data_count) - 1;
process(ACLK) begin
if ACLK'event and ACLK='1' then
if reset='1' then
write_count <= (others => '0');
awlen <= (others => '0');
else
if wr_main_cs = write_state and wrt_cs=idle_wr then -- wr_main_cs がwrite_state になった最初の1クロック
if C_UPSIDE_DOWN = 0 then -- 正常表示の場合
write_count <= std_logic_vector(pfifo_rd_dcount_dec(7 downto 0));
awlen <= std_logic_vector(pfifo_rd_dcount_dec(7 downto 0));
else -- 上下反転する場合はシングル転送
write_count <= std_logic_vector(to_unsigned(0, write_count'length));
awlen <= std_logic_vector(to_unsigned(0, awlen'length));
end if;
elsif wrt_wv_cs=wvalid_assert and M_AXI_WREADY='1' and unsigned(write_count)/=0 then -- １つデータ転送出来た
write_count <= std_logic_vector(unsigned(write_count) - 1);
end if;
end if;
end if;
end process;
-- wlastの処理
process(ACLK) begin
if ACLK'event and ACLK='1' then
if reset='1' then
wlast <= '0';
else
if wr_main_cs = write_state and wrt_cs=idle_wr then -- Wrire Transaction を開始する際に、
if C_UPSIDE_DOWN = 0 then -- 正常表示の場合
if unsigned(pfifo_rd_data_count)=1 then -- pfifo_rd_data_count が1の時はデータ転送の最初からwlast をアサートする
wlast <= '1';
end if;
else -- 上下反転する場合はシングル転送
wlast <= '1';
end if;
elsif wrt_wv_cs=wvalid_assert and unsigned(write_count)=1 and M_AXI_WREADY='1' then -- awlen が0で無い時はwrite_count が1でM_AXI_WREADY='1'の時、つまりwrite_count が0の時にwlastをアサートする
wlast <= '1';
elsif wrt_wv_cs=wvalid_assert and unsigned(write_count)=0 and M_AXI_WREADY='1' then -- データ転送が終了なのでwlast を0にする
wlast <= '0';
end if;
end if;
end if;
end process;
M_AXI_WLAST <= wlast;
-- wr_error の処理、M_AXI_BRESPがRESP_OKAY以外の時にwr_errorを点灯する
process(ACLK) begin
if ACLK'event and ACLK='1' then
if reset='1' then
wr_error <= '0';
else
if wrt_cs=bready_assert and M_AXI_BVALID='1' and M_AXI_BRESP/=RESP_OKAY then
wr_error <= '1';
end if;
end if;
end if;
end process;
-- Readは無し
M_AXI_ARID <= "0";
M_AXI_ARLEN <= (others => '0');
M_AXI_ARSIZE <= "010"; -- 4bytes
M_AXI_ARBURST <= "01"; -- INCR
M_AXI_ARLOCK <= "00"; -- Normal Access
M_AXI_ARCACHE <= "0010"; -- Normal Non-cacheable Non-bufferable
M_AXI_ARPROT <= "000"; -- Data access, Secure access, Unprivileged access
M_AXI_ARQOS <= "0000"; -- default
M_AXI_ARUSER <= "0";
M_AXI_ARADDR <= (others => '0');
M_AXI_ARVALID <= '0';
M_AXI_RREADY <= '0';
end implementation;
// MT9D111カメラコントローラ
// MT9D111_cam_cont.v
// 2012/12/26
//
`default_nettype none
module mt9d111_cam_cont # (
parameter DISPLAY_START_ADDRESS = 32'h10000000, // Frame Buffer Start Address
parameter integer UPSIDE_DOWN = 0 // 1 = 上下反転、0 = 正常
)(
input wire aclk,
input wire areset,
input wire pclk,
input wire preset,
input wire pclk_from_pll,
output wire xclk,
input wire line_valid,
input wire frame_valid,
input wire [7:0] cam_data,
output wire standby,
output wire [31:0] paddr,
input wire pfifo_rd_en,
output wire [63:0] pfifo_dout,
output wire pfifo_empty,
output wire pfifo_almost_empty,
output wire [9:0] pfifo_rd_data_count,
output wire pfifo_overflow,
output wire pfifo_underflow
);
`include "./disp_timing_parameters.vh"
// Frame Buffer End Address
localparam DISPLAY_END_ADDRESS = DISPLAY_START_ADDRESS + (H_ACTIVE_VIDEO * V_ACTIVE_VIDEO)*4 - 8; // 最後のピクセル、1ピクセル = 4バイトで、64ビットバス幅なので、8バイトごと
reg line_valid_1d;
reg frame_valid_1d;
reg [7:0] cam_data_1d;
reg line_valid_1d_odd;
reg line_v_1d_odd_1d;
reg [63:0] rgb565;
wire pfifo_full, pfifo_almost_full;
reg frame_valid_1d_aclk_1d, frame_valid_1d_aclk_2d;
parameter [1:0] IDLE_ADDR_RST = 2'b00,
ADDR_RST = 2'b01,
ADDR_RST_HOLD = 2'b11;
reg [1:0] addr_rst_cs;
reg [31:0] paddr_reg;
reg rgb565_2nd;
assign standby = 1'b0;
// MT9D111 へのクロックを出力 (xclk)
ODDR #(
.DDR_CLK_EDGE("SAME_EDGE"), // "OPPOSITE_EDGE" or "SAME_EDGE"
.INIT(1'b0), // Initial value of Q: 1'b0 or 1'b1
.SRTYPE("SYNC") // Set/Reset type: "SYNC" or "ASYNC"
) ODDR_inst (
.Q(xclk), // 1-bit DDR output
.C(pclk_from_pll), // 1-bit clock input
.CE(1'b1), // 1-bit clock enable input
.D1(1'b1), // 1-bit data input (positive edge)
.D2(1'b0), // 1-bit data input (negative edge)
.R(1'b0), // 1-bit reset
.S(1'b0) // 1-bit set
);
// 入力信号を一旦ラッチする
always @(posedge pclk) begin
if (preset) begin
line_valid_1d <= 1'b0;
frame_valid_1d <= 1'b0;
cam_data_1d <= 8'd0;
end else begin
line_valid_1d <= line_valid;
frame_valid_1d <= frame_valid;
cam_data_1d <= cam_data;
end
end
// frame_valid_1d をaclk でラッチする
always @(posedge aclk) begin
if (areset) begin
frame_valid_1d_aclk_1d <= 1'b0;
frame_valid_1d_aclk_2d <= 1'b0;
end else begin
frame_valid_1d_aclk_1d <= frame_valid_1d;
frame_valid_1d_aclk_2d <= frame_valid_1d_aclk_1d;
end
end
// line_valid_1d が偶数か奇数かをカウント
always @(posedge pclk) begin
if (preset)
line_valid_1d_odd <= 1'b0;
else begin
if (line_valid_1d)
line_valid_1d_odd <= ~line_valid_1d_odd;
else
line_valid_1d_odd <= 1'b0;
end
end
// rgb565でラッチしているので、line_valid_1d_odd を1クロック遅延する
always @(posedge pclk) begin
if (preset)
line_v_1d_odd_1d <= 1'b0;
else
line_v_1d_odd_1d <= line_valid_1d_odd;
end
// 2番めのRGB565を示す。64ビット長のFIFOに入れるのに2ピクセル集めてから非同期FIFOにWriteする
always @(posedge pclk) begin
if (preset)
rgb565_2nd <= 1'b0;
else begin
if (line_valid_1d_odd)
rgb565_2nd <= ~rgb565_2nd;
end
end
// addressの生成
always @(posedge aclk) begin
if (areset) begin
if (UPSIDE_DOWN==0) // 正常、それ以外は上下反転
paddr_reg <= DISPLAY_START_ADDRESS;
else // 上下反転
paddr_reg <= DISPLAY_END_ADDRESS;
end else begin
if (pfifo_rd_en) begin
if (UPSIDE_DOWN==0) // 正常
paddr_reg <= paddr_reg + 32'd8;
else // 上下反転
paddr_reg <= paddr_reg - 32'd8;
end else if (addr_rst_cs==ADDR_RST) begin // frame_valid が0になって、pfifoにデータが無くなった時にアドレスをクリア
if (UPSIDE_DOWN==0) // 正常、それ以外は上下反転
paddr_reg <= DISPLAY_START_ADDRESS;
else // 上下反転
paddr_reg <= DISPLAY_END_ADDRESS;
end
end
end
assign paddr = paddr_reg;
// address をリセットするためのステートマシン
always @(posedge aclk) begin
if (areset)
addr_rst_cs <= IDLE_ADDR_RST;
else begin
case (addr_rst_cs)
IDLE_ADDR_RST :
if (~frame_valid_1d_aclk_2d & pfifo_empty)
addr_rst_cs <= ADDR_RST;
ADDR_RST :
addr_rst_cs <= ADDR_RST_HOLD;
ADDR_RST_HOLD :
if (frame_valid_1d_aclk_2d)
addr_rst_cs <= IDLE_ADDR_RST;
endcase
end
end
// RGB565 のデータを保存する。正常と上下反転ではバイト配列が異なる
always @(posedge pclk) begin
if (preset)
rgb565 <= 32'd0;
else begin
if (UPSIDE_DOWN==0) begin // 正常、それ以外は上下反転
case ({rgb565_2nd, line_valid_1d_odd})
2'b00 : // 1番目
rgb565[63:45] <= {8'd0, cam_data_1d[7:3], 3'b000, cam_data_1d[2:0]}; // cam_data_1d = R7 R6 R5 R4 R3 G7 G6 G5
2'b01 : // 2番目
rgb565[44:32] <= {cam_data_1d[7:5], 2'b00, cam_data_1d[4:0], 3'b000}; // cam_data_1d = G4 G3 G2 B7 B6 B5 B4 B3
2'b10 : // 3番目
rgb565[31:13] <= {8'd0, cam_data_1d[7:3], 3'b000, cam_data_1d[2:0]}; // cam_data_1d = R7 R6 R5 R4 R3 G7 G6 G5
2'b11 : // 4番目
rgb565[12:0] <= {cam_data_1d[7:5], 2'b00, cam_data_1d[4:0], 3'b000}; // cam_data_1d = G4 G3 G2 B7 B6 B5 B4 B3
endcase
end else begin // 上下反転
case ({rgb565_2nd, line_valid_1d_odd})
2'b00 : // 1番目
rgb565[31:13] <= {8'd0, cam_data_1d[7:3], 3'b000, cam_data_1d[2:0]}; // cam_data_1d = R7 R6 R5 R4 R3 G7 G6 G5
2'b01 : // 2番目
rgb565[12:0] <= {cam_data_1d[7:5], 2'b00, cam_data_1d[4:0], 3'b000}; // cam_data_1d = G4 G3 G2 B7 B6 B5 B4 B3
2'b10 : // 3番目
rgb565[63:45] <= {8'd0, cam_data_1d[7:3], 3'b000, cam_data_1d[2:0]}; // cam_data_1d = R7 R6 R5 R4 R3 G7 G6 G5
2'b11 : // 4番目
rgb565[44:32] <= {cam_data_1d[7:5], 2'b00, cam_data_1d[4:0], 3'b000}; // cam_data_1d = G4 G3 G2 B7 B6 B5 B4 B3
endcase
end
end
end
// pixel FIFO をインスタンスする
pixel_fifo pfifo (
.rst(areset), // input rst
.wr_clk(pclk), // input wr_clk
.rd_clk(aclk), // input rd_clk
.din(rgb565), // input [63 : 0] din
.wr_en(line_v_1d_odd_1d & ~rgb565_2nd), // input wr_en, 2つのピクセルが揃うには4クロック掛かる
.rd_en(pfifo_rd_en), // input rd_en
.dout(pfifo_dout), // output [63 : 0] dout
.full(pfifo_full), // output full
.almost_full(pfifo_almost_full), // output almost_full
.overflow(pfifo_overflow), // output overflow
.empty(pfifo_empty), // output empty
.almost_empty(pfifo_almost_empty), // output almost_empty
.underflow(pfifo_underflow), // output underflow
.rd_data_count(pfifo_rd_data_count) // output [9 : 0] rd_data_count
);
endmodule
`default_nettype wire
##############################################################
#
# Xilinx Core Generator version 14.4
# Date: Wed Jan 16 12:27:21 2013
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# Generated from component: xilinx.com:ip:fifo_generator:9.3
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = Verilog
SET device = xc7z020
SET devicefamily = zynq
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = clg484
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -1
SET verilogsim = true
SET vhdlsim = false
# END Project Options
# BEGIN Select
SELECT FIFO_Generator xilinx.com:ip:fifo_generator:9.3
# END Select
# BEGIN Parameters
CSET add_ngc_constraint_axi=false
CSET almost_empty_flag=true
CSET almost_full_flag=true
CSET aruser_width=1
CSET awuser_width=1
CSET axi_address_width=32
CSET axi_data_width=64
CSET axi_type=AXI4_Stream
CSET axis_type=FIFO
CSET buser_width=1
CSET clock_enable_type=Slave_Interface_Clock_Enable
CSET clock_type_axi=Common_Clock
CSET component_name=pixel_fifo
CSET data_count=false
CSET data_count_width=9
CSET disable_timing_violations=false
CSET disable_timing_violations_axi=false
CSET dout_reset_value=0
CSET empty_threshold_assert_value=4
CSET empty_threshold_assert_value_axis=1022
CSET empty_threshold_assert_value_rach=1022
CSET empty_threshold_assert_value_rdch=1022
CSET empty_threshold_assert_value_wach=1022
CSET empty_threshold_assert_value_wdch=1022
CSET empty_threshold_assert_value_wrch=1022
CSET empty_threshold_negate_value=5
CSET enable_aruser=false
CSET enable_awuser=false
CSET enable_buser=false
CSET enable_common_overflow=false
CSET enable_common_underflow=false
CSET enable_data_counts_axis=false
CSET enable_data_counts_rach=false
CSET enable_data_counts_rdch=false
CSET enable_data_counts_wach=false
CSET enable_data_counts_wdch=false
CSET enable_data_counts_wrch=false
CSET enable_ecc=false
CSET enable_ecc_axis=false
CSET enable_ecc_rach=false
CSET enable_ecc_rdch=false
CSET enable_ecc_wach=false
CSET enable_ecc_wdch=false
CSET enable_ecc_wrch=false
CSET enable_read_channel=false
CSET enable_read_pointer_increment_by2=false
CSET enable_reset_synchronization=true
CSET enable_ruser=false
CSET enable_tdata=false
CSET enable_tdest=false
CSET enable_tid=false
CSET enable_tkeep=false
CSET enable_tlast=false
CSET enable_tready=true
CSET enable_tstrobe=false
CSET enable_tuser=false
CSET enable_write_channel=false
CSET enable_wuser=false
CSET fifo_application_type_axis=Data_FIFO
CSET fifo_application_type_rach=Data_FIFO
CSET fifo_application_type_rdch=Data_FIFO
CSET fifo_application_type_wach=Data_FIFO
CSET fifo_application_type_wdch=Data_FIFO
CSET fifo_application_type_wrch=Data_FIFO
CSET fifo_implementation=Independent_Clocks_Block_RAM
CSET fifo_implementation_axis=Common_Clock_Block_RAM
CSET fifo_implementation_rach=Common_Clock_Distributed_RAM
CSET fifo_implementation_rdch=Common_Clock_Block_RAM
CSET fifo_implementation_wach=Common_Clock_Distributed_RAM
CSET fifo_implementation_wdch=Common_Clock_Block_RAM
CSET fifo_implementation_wrch=Common_Clock_Distributed_RAM
CSET full_flags_reset_value=1
CSET full_threshold_assert_value=511
CSET full_threshold_assert_value_axis=1023
CSET full_threshold_assert_value_rach=1023
CSET full_threshold_assert_value_rdch=1023
CSET full_threshold_assert_value_wach=1023
CSET full_threshold_assert_value_wdch=1023
CSET full_threshold_assert_value_wrch=1023
CSET full_threshold_negate_value=510
CSET id_width=4
CSET inject_dbit_error=false
CSET inject_dbit_error_axis=false
CSET inject_dbit_error_rach=false
CSET inject_dbit_error_rdch=false
CSET inject_dbit_error_wach=false
CSET inject_dbit_error_wdch=false
CSET inject_dbit_error_wrch=false
CSET inject_sbit_error=false
CSET inject_sbit_error_axis=false
CSET inject_sbit_error_rach=false
CSET inject_sbit_error_rdch=false
CSET inject_sbit_error_wach=false
CSET inject_sbit_error_wdch=false
CSET inject_sbit_error_wrch=false
CSET input_data_width=64
CSET input_depth=512
CSET input_depth_axis=1024
CSET input_depth_rach=16
CSET input_depth_rdch=1024
CSET input_depth_wach=16
CSET input_depth_wdch=1024
CSET input_depth_wrch=16
CSET interface_type=Native
CSET output_data_width=64
CSET output_depth=512
CSET overflow_flag=true
CSET overflow_flag_axi=false
CSET overflow_sense=Active_High
CSET overflow_sense_axi=Active_High
CSET performance_options=First_Word_Fall_Through
CSET programmable_empty_type=No_Programmable_Empty_Threshold
CSET programmable_empty_type_axis=No_Programmable_Empty_Threshold
CSET programmable_empty_type_rach=No_Programmable_Empty_Threshold
CSET programmable_empty_type_rdch=No_Programmable_Empty_Threshold
CSET programmable_empty_type_wach=No_Programmable_Empty_Threshold
CSET programmable_empty_type_wdch=No_Programmable_Empty_Threshold
CSET programmable_empty_type_wrch=No_Programmable_Empty_Threshold
CSET programmable_full_type=No_Programmable_Full_Threshold
CSET programmable_full_type_axis=No_Programmable_Full_Threshold
CSET programmable_full_type_rach=No_Programmable_Full_Threshold
CSET programmable_full_type_rdch=No_Programmable_Full_Threshold
CSET programmable_full_type_wach=No_Programmable_Full_Threshold
CSET programmable_full_type_wdch=No_Programmable_Full_Threshold
CSET programmable_full_type_wrch=No_Programmable_Full_Threshold
CSET rach_type=FIFO
CSET rdch_type=FIFO
CSET read_clock_frequency=1
CSET read_data_count=true
CSET read_data_count_width=10
CSET register_slice_mode_axis=Fully_Registered
CSET register_slice_mode_rach=Fully_Registered
CSET register_slice_mode_rdch=Fully_Registered
CSET register_slice_mode_wach=Fully_Registered
CSET register_slice_mode_wdch=Fully_Registered
CSET register_slice_mode_wrch=Fully_Registered
CSET reset_pin=true
CSET reset_type=Asynchronous_Reset
CSET ruser_width=1
CSET synchronization_stages=2
CSET synchronization_stages_axi=2
CSET tdata_width=64
CSET tdest_width=4
CSET tid_width=8
CSET tkeep_width=4
CSET tstrb_width=4
CSET tuser_width=4
CSET underflow_flag=true
CSET underflow_flag_axi=false
CSET underflow_sense=Active_High
CSET underflow_sense_axi=Active_High
CSET use_clock_enable=false
CSET use_dout_reset=true
CSET use_embedded_registers=true
CSET use_extra_logic=true
CSET valid_flag=false
CSET valid_sense=Active_High
CSET wach_type=FIFO
CSET wdch_type=FIFO
CSET wrch_type=FIFO
CSET write_acknowledge_flag=false
CSET write_acknowledge_sense=Active_High
CSET write_clock_frequency=1
CSET write_data_count=false
CSET write_data_count_width=10
CSET wuser_width=1
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2012-11-19T12:39:56Z
# END Extra information
GENERATE
# CRC: 73737d3d
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