## NOTE: Do not edit this file.
## Autogenerated by ProjNav (creatfdo.tcl) on Thu Jun 15 18:34:07 東京 (標準時) 2006
##
vlib work
vlog "dcm133.v"
vcom -explicit -93 "IDELAY_VARIABLE_TEST.vhd"
vcom -explicit -93 "IDELAY_VARIABLE_TEST_tb.vhd"
vlog "C:/HDL/Xilinx/verilog/src/glbl.v"
vsim -t 1ps -L xilinxcorelib_ver -L unisims_ver -lib work IDELAY_VARIABLE_TEST_tb glbl
do {IDELAY_VARIABLE_TEST_tb.udo}
view wave
add wave *
add wave /glbl/GSR
view structure
view signals
run 1000ns
## NOTE: Do not edit this file.
## Autogenerated by ProjNav (creatfdo.tcl) on Thu Jun 15 19:32:23 東京 (標準時) 2006
##
vlib work
vcom -explicit -93 "dcm133.vhd"
vcom -explicit -93 "IDELAY_VARIABLE_TEST.vhd"
vcom -explicit -93 "IDELAY_VARIABLE_TEST_tb.vhd"
vsim -t 1ps -lib work IDELAY_VARIABLE_TEST_tb
do {IDELAY_VARIABLE_TEST_tb.udo}
view wave
add wave *
view structure
view signals
run 1000ns
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