FC2カウンター FPGAの部屋 ZedBoard AXI4 Lite Slave 演習5(MPD と PAO ファイルの公開)
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ZedBoard AXI4 Lite Slave 演習5(MPD と PAO ファイルの公開)

ZedBoard AXI4 Lite Slave 演習4(Verilog HDL と UCF ソースの公開)”の続き。

今回は、MPDファイルとPAOファイルを貼っておく。MUIファイルはテンプレートのまま使用している。
まずは、MPDファイルを貼っておく (led8_axi_lite_slave_v2_1_0.mpd) 。

#-- DISCLAIMER OF LIABILITY
#--
#-- This file contains proprietary and confidential information of
#-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
#-- from Xilinx, and may be used, copied and/or disclosed only
#-- pursuant to the terms of a valid license agreement with Xilinx.
#--
#-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
#-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
#-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
#-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
#-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
#-- does not warrant that functions included in the Materials will
#-- meet the requirements of Licensee, or that the operation of the
#-- Materials will be uninterrupted or error-free, or that defects
#-- in the Materials will be corrected. Furthermore, Xilinx does
#-- not warrant or make any representations regarding use, or the
#-- results of the use, of the Materials in terms of correctness,
#-- accuracy, reliability or otherwise.
#--
#-- Xilinx products are not designed or intended to be fail-safe,
#-- or for use in any application requiring fail-safe performance,
#-- such as life-support or safety devices or systems, Class III
#-- medical devices, nuclear facilities, applications related to
#-- the deployment of airbags, or any other applications that could
#-- lead to death, personal injury or severe property or
#-- environmental damage (individually and collectively, "critical
#-- applications"). Customer assumes the sole risk and liability
#-- of any use of Xilinx products in critical applications,
#-- subject only to applicable laws and regulations governing
#-- limitations on product liability.
#--
#-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
#--
#-- This disclaimer and copyright notice must be retained as part
#-- of this file at all times.
#--
###################################################################
##
## Name : led8_axi_lite_slave
## Desc : Microprocessor Peripheral Description
## : Automatically generated by PsfUtility
##
###################################################################

BEGIN led8_axi_lite_slave

## Peripheral Options
OPTION IPTYPE = PERIPHERAL
OPTION IMP_NETLIST = TRUE
OPTION STYLE = HDL
OPTION DESC = LED8 AXI Lite Slave
OPTION LONG_DESC = LED 8bit AXI4-Lite Slave
OPTION HDL = MIXED
OPTION RUN_NGCBUILD = FALSE

## Bus Interfaces
BUS_INTERFACE BUS = S_AXI, BUS_STD = AXI, BUS_TYPE = SLAVE

## Generics for VHDL or Parameters for Verilog
PARAMETER C_S_AXI_ADDR_WIDTH = 32, DT = integer, ASSIGNMENT = CONSTANT, BUS = S_AXI
PARAMETER C_S_AXI_DATA_WIDTH = 32, DT = integer, ASSIGNMENT = CONSTANT, BUS = S_AXI
PARAMETER C_S_AXI_PROTOCOL = AXI4Lite, DT = string, TYPE = NON_HDL, ASSIGNMENT = CONSTANT, BUS = S_AXI
PARAMETER C_S_AXI_SUPPORTS_READ = 1, DT = integer, RANGE = (0,1), TYPE = NON_HDL, ASSIGNMENT = OPTIONAL_UPDATE, BUS = S_AXI
PARAMETER C_S_AXI_SUPPORTS_WRITE = 1, DT = integer, RANGE = (0,1), TYPE = NON_HDL, ASSIGNMENT = OPTIONAL_UPDATE, BUS = S_AXI
PARAMETER C_S_AXI_NUM_ADDR_RANGES = 1, BUS = S_AXI, DT = INTEGER, ASSIGNMENT = OPTIONAL_UPDATE, TYPE = NON_HDL, RANGE = (1:4)
PARAMETER C_S_AXI_RNG00_BASEADDR = 0xFFFFFFFF, BUS = S_AXI, DT = std_logic_vector, ADDRESS = BASE, PAIR = C_S_AXI_RNG00_HIGHADDR, ISVALID = (C_S_AXI_NUM_ADDR_RANGES >= 1), TYPE = NON_HDL, MIN_SIZE = 0x1000
PARAMETER C_S_AXI_RNG00_HIGHADDR = 0x00000000, BUS = S_AXI, DT = std_logic_vector, ADDRESS = HIGH, PAIR = C_S_AXI_RNG00_BASEADDR, ISVALID = (C_S_AXI_NUM_ADDR_RANGES >= 1), TYPE = NON_HDL
PARAMETER C_S_AXI_RNG01_BASEADDR = 0xFFFFFFFF, BUS = S_AXI, DT = std_logic_vector, ADDRESS = BASE, PAIR = C_S_AXI_RNG01_HIGHADDR, ISVALID = (C_S_AXI_NUM_ADDR_RANGES >= 2), TYPE = NON_HDL, MIN_SIZE = 0x1000
PARAMETER C_S_AXI_RNG01_HIGHADDR = 0x00000000, BUS = S_AXI, DT = std_logic_vector, ADDRESS = HIGH, PAIR = C_S_AXI_RNG01_BASEADDR, ISVALID = (C_S_AXI_NUM_ADDR_RANGES >= 2), TYPE = NON_HDL
PARAMETER C_S_AXI_RNG02_BASEADDR = 0xFFFFFFFF, BUS = S_AXI, DT = std_logic_vector, ADDRESS = BASE, PAIR = C_S_AXI_RNG02_HIGHADDR, ISVALID = (C_S_AXI_NUM_ADDR_RANGES >= 3), TYPE = NON_HDL, MIN_SIZE = 0x1000
PARAMETER C_S_AXI_RNG02_HIGHADDR = 0x00000000, BUS = S_AXI, DT = std_logic_vector, ADDRESS = HIGH, PAIR = C_S_AXI_RNG02_BASEADDR, ISVALID = (C_S_AXI_NUM_ADDR_RANGES >= 3), TYPE = NON_HDL
PARAMETER C_S_AXI_RNG03_BASEADDR = 0xFFFFFFFF, BUS = S_AXI, DT = std_logic_vector, ADDRESS = BASE, PAIR = C_S_AXI_RNG03_HIGHADDR, ISVALID = (C_S_AXI_NUM_ADDR_RANGES >= 4), TYPE = NON_HDL, MIN_SIZE = 0x1000
PARAMETER C_S_AXI_RNG03_HIGHADDR = 0x00000000, BUS = S_AXI, DT = std_logic_vector, ADDRESS = HIGH, PAIR = C_S_AXI_RNG03_BASEADDR, ISVALID = (C_S_AXI_NUM_ADDR_RANGES >= 4), TYPE = NON_HDL

## Ports
PORT ACLK = "", BUS = S_AXI, DIR = I, SIGIS = CLK
PORT ARESETN = ARESETN, BUS = S_AXI, DIR = I, SIGIS = RST
PORT S_AXI_AWADDR = AWADDR, BUS = S_AXI, DIR = I, VEC = [(C_S_AXI_ADDR_WIDTH-1):0]
PORT S_AXI_AWPROT = AWPROT, BUS = S_AXI, DIR = I, VEC = [2:0]
PORT S_AXI_AWVALID = AWVALID, BUS = S_AXI, DIR = I
PORT S_AXI_AWREADY = AWREADY, BUS = S_AXI, DIR = O
PORT S_AXI_WDATA = WDATA, BUS = S_AXI, DIR = I, VEC = [(C_S_AXI_DATA_WIDTH-1):0]
PORT S_AXI_WSTRB = WSTRB, BUS = S_AXI, DIR = I, VEC = [((C_S_AXI_DATA_WIDTH/8) -1):0]
PORT S_AXI_WVALID = WVALID, BUS = S_AXI, DIR = I
PORT S_AXI_WREADY = WREADY, BUS = S_AXI, DIR = O
PORT S_AXI_BRESP = BRESP, BUS = S_AXI, DIR = O, VEC = [1:0]
PORT S_AXI_BVALID = BVALID, BUS = S_AXI, DIR = O
PORT S_AXI_BREADY = BREADY, BUS = S_AXI, DIR = I
PORT S_AXI_ARADDR = ARADDR, BUS = S_AXI, DIR = I, VEC = [(C_S_AXI_ADDR_WIDTH-1):0
PORT S_AXI_ARPROT = ARPROT, BUS = S_AXI, DIR = I, VEC = [2:0]
PORT S_AXI_ARVALID = ARVALID, BUS = S_AXI, DIR = I
PORT S_AXI_ARREADY = ARREADY, BUS = S_AXI, DIR = O
PORT S_AXI_RDATA = RDATA, BUS = S_AXI, DIR = O, VEC = [(C_S_AXI_DATA_WIDTH-1):0]
PORT S_AXI_RRESP = RRESP, BUS = S_AXI, DIR = O, VEC = [1:0]
PORT S_AXI_RVALID = RVALID, BUS = S_AXI, DIR = O
PORT S_AXI_RREADY = RREADY, BUS = S_AXI, DIR = I

PORT LED8bit = "", DIR = O, VEC = [7:0]
END


次に、PAO ファイルを貼っておく (led8_axi_lite_slave_v2_1_0.pao)。

## -- DISCLAIMER OF LIABILITY
## --
## -- This file contains proprietary and confidential information of
## -- Xilinx, Inc. ("Xilinx"), that is distributed under a license
## -- from Xilinx, and may be used, copied and/or disclosed only
## -- pursuant to the terms of a valid license agreement with Xilinx.
## --
## -- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
## -- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
## -- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
## -- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
## -- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
## -- does not warrant that functions included in the Materials will
## -- meet the requirements of Licensee, or that the operation of the
## -- Materials will be uninterrupted or error-free, or that defects
## -- in the Materials will be corrected. Furthermore, Xilinx does
## -- not warrant or make any representations regarding use, or the
## -- results of the use, of the Materials in terms of correctness,
## -- accuracy, reliability or otherwise.
## --
## -- Xilinx products are not designed or intended to be fail-safe,
## -- or for use in any application requiring fail-safe performance,
## -- such as life-support or safety devices or systems, Class III
## -- medical devices, nuclear facilities, applications related to
## -- the deployment of airbags, or any other applications that could
## -- lead to death, personal injury or severe property or
## -- environmental damage (individually and collectively, "critical
## -- applications"). Customer assumes the sole risk and liability
## -- of any use of Xilinx products in critical applications,
## -- subject only to applicable laws and regulations governing
## -- limitations on product liability.
## --
## -- Copyright 2009 Xilinx, Inc.
## -- All rights reserved.
## --
## -- This disclaimer and copyright notice must be retained as part
## -- of this file at all times.
##
###############################################################################
##
## axi_lite_slave_v2_1_0.pao
##
## Peripheral Analyze Order File
##
##
###############################################################################


lib led8_axi_lite_slave_v1_00_a led8_axi_lite_slave.v verilog

  1. 2013年12月19日 04:50 |
  2. AXI4バスの演習資料
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