FC2カウンター FPGAの部屋 Vivado 2013.4でAXI VDMAを使ったカメラ表示回路の作製14(ハードウェアのデバック2)
FC2ブログ

FPGAやCPLDの話題やFPGA用のツールの話題などです。 マニアックです。 日記も書きます。

FPGAの部屋

FPGAの部屋の有用と思われるコンテンツのまとめサイトを作りました。Xilinx ISEの初心者の方には、FPGAリテラシーおよびチュートリアルのページをお勧めいたします。

Vivado 2013.4でAXI VDMAを使ったカメラ表示回路の作製14(ハードウェアのデバック2)

Vivado 2013.4でAXI VDMAを使ったカメラ表示回路の作製13(ハードウェアのデバック1)”の続き。

前回はデバックを行うネットを指定してILAコアを挿入し、インプリメントを行ったがタイミングエラーが発生した。
今回は、クロック間のタイミング制約を設定して、インプリメントを行い、ハードウェアをエクスポートしてSDKを立ち上げる。

・timing.xdc に pclk と clk_fpga_0 間の制約を無視するように、false_path 制約を追加した。
Cam_VDMA_172_140130.png

set_false_path -from [get_clocks pclk] -to [get_clocks clk_fpga_0]


・これでもう一度インプリメントを行ったところ、タイミングエラーは無くなった。
Cam_VDMA_173_140130.png

・timing.xdc には、ILAの制約が入っていた。ILAの制約を下に示す。

create_debug_core u_ila_0 labtools_ila_v3
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
set_property ALL_PROBE_SAME_MU_CNT 4 [get_debug_cores u_ila_0]
set_property C_ADV_TRIGGER true [get_debug_cores u_ila_0]
set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_0]
set_property C_EN_STRG_QUAL true [get_debug_cores u_ila_0]
set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
set_property port_width 1 [get_debug_ports u_ila_0/clk]
connect_debug_port u_ila_0/clk [get_nets [list CamD_VDMA_i/processing_system7_0/FCLK_CLK0]]
set_property port_width 4 [get_debug_ports u_ila_0/probe0]
connect_debug_port u_ila_0/probe0 [get_nets [list {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_ARCACHE[0]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_ARCACHE[1]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_ARCACHE[2]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_ARCACHE[3]}]]
create_debug_core u_ila_1 labtools_ila_v3
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_1]
set_property ALL_PROBE_SAME_MU_CNT 4 [get_debug_cores u_ila_1]
set_property C_ADV_TRIGGER true [get_debug_cores u_ila_1]
set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_1]
set_property C_EN_STRG_QUAL true [get_debug_cores u_ila_1]
set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_1]
set_property C_TRIGIN_EN false [get_debug_cores u_ila_1]
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_1]
set_property port_width 1 [get_debug_ports u_ila_1/clk]
connect_debug_port u_ila_1/clk [get_nets [list CamD_VDMA_i/processing_system7_0_FCLK_CLK0]]
set_property port_width 32 [get_debug_ports u_ila_1/probe0]
connect_debug_port u_ila_1/probe0 [get_nets [list {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_ARADDR[0]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_ARADDR[1]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_ARADDR[2]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_ARADDR[3]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_ARADDR[4]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_ARADDR[5]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_ARADDR[6]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_ARADDR[7]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_ARADDR[8]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_ARADDR[9]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_ARADDR[10]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_ARADDR[11]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_ARADDR[12]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_ARADDR[13]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_ARADDR[14]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_ARADDR[15]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_ARADDR[16]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_ARADDR[17]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_ARADDR[18]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_ARADDR[19]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_ARADDR[20]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_ARADDR[21]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_ARADDR[22]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_ARADDR[23]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_ARADDR[24]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_ARADDR[25]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_ARADDR[26]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_ARADDR[27]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_ARADDR[28]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_ARADDR[29]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_ARADDR[30]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_ARADDR[31]}]]
create_debug_core u_ila_2 labtools_ila_v3
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_2]
set_property ALL_PROBE_SAME_MU_CNT 4 [get_debug_cores u_ila_2]
set_property C_ADV_TRIGGER true [get_debug_cores u_ila_2]
set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_2]
set_property C_EN_STRG_QUAL true [get_debug_cores u_ila_2]
set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_2]
set_property C_TRIGIN_EN false [get_debug_cores u_ila_2]
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_2]
set_property port_width 1 [get_debug_ports u_ila_2/clk]
connect_debug_port u_ila_2/clk [get_nets [list CamD_VDMA_i/processing_system7_0_FCLK_CLK2]]
set_property port_width 32 [get_debug_ports u_ila_2/probe0]
connect_debug_port u_ila_2/probe0 [get_nets [list {CamD_VDMA_i/axi_vdma_0_M_AXIS_MM2S_TDATA[0]} {CamD_VDMA_i/axi_vdma_0_M_AXIS_MM2S_TDATA[1]} {CamD_VDMA_i/axi_vdma_0_M_AXIS_MM2S_TDATA[2]} {CamD_VDMA_i/axi_vdma_0_M_AXIS_MM2S_TDATA[3]} {CamD_VDMA_i/axi_vdma_0_M_AXIS_MM2S_TDATA[4]} {CamD_VDMA_i/axi_vdma_0_M_AXIS_MM2S_TDATA[5]} {CamD_VDMA_i/axi_vdma_0_M_AXIS_MM2S_TDATA[6]} {CamD_VDMA_i/axi_vdma_0_M_AXIS_MM2S_TDATA[7]} {CamD_VDMA_i/axi_vdma_0_M_AXIS_MM2S_TDATA[8]} {CamD_VDMA_i/axi_vdma_0_M_AXIS_MM2S_TDATA[9]} {CamD_VDMA_i/axi_vdma_0_M_AXIS_MM2S_TDATA[10]} {CamD_VDMA_i/axi_vdma_0_M_AXIS_MM2S_TDATA[11]} {CamD_VDMA_i/axi_vdma_0_M_AXIS_MM2S_TDATA[12]} {CamD_VDMA_i/axi_vdma_0_M_AXIS_MM2S_TDATA[13]} {CamD_VDMA_i/axi_vdma_0_M_AXIS_MM2S_TDATA[14]} {CamD_VDMA_i/axi_vdma_0_M_AXIS_MM2S_TDATA[15]} {CamD_VDMA_i/axi_vdma_0_M_AXIS_MM2S_TDATA[16]} {CamD_VDMA_i/axi_vdma_0_M_AXIS_MM2S_TDATA[17]} {CamD_VDMA_i/axi_vdma_0_M_AXIS_MM2S_TDATA[18]} {CamD_VDMA_i/axi_vdma_0_M_AXIS_MM2S_TDATA[19]} {CamD_VDMA_i/axi_vdma_0_M_AXIS_MM2S_TDATA[20]} {CamD_VDMA_i/axi_vdma_0_M_AXIS_MM2S_TDATA[21]} {CamD_VDMA_i/axi_vdma_0_M_AXIS_MM2S_TDATA[22]} {CamD_VDMA_i/axi_vdma_0_M_AXIS_MM2S_TDATA[23]} {CamD_VDMA_i/axi_vdma_0_M_AXIS_MM2S_TDATA[24]} {CamD_VDMA_i/axi_vdma_0_M_AXIS_MM2S_TDATA[25]} {CamD_VDMA_i/axi_vdma_0_M_AXIS_MM2S_TDATA[26]} {CamD_VDMA_i/axi_vdma_0_M_AXIS_MM2S_TDATA[27]} {CamD_VDMA_i/axi_vdma_0_M_AXIS_MM2S_TDATA[28]} {CamD_VDMA_i/axi_vdma_0_M_AXIS_MM2S_TDATA[29]} {CamD_VDMA_i/axi_vdma_0_M_AXIS_MM2S_TDATA[30]} {CamD_VDMA_i/axi_vdma_0_M_AXIS_MM2S_TDATA[31]}]]
create_debug_core u_ila_3 labtools_ila_v3
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_3]
set_property ALL_PROBE_SAME_MU_CNT 4 [get_debug_cores u_ila_3]
set_property C_ADV_TRIGGER true [get_debug_cores u_ila_3]
set_property C_DATA_DEPTH 1024 [get_debug_cores u_ila_3]
set_property C_EN_STRG_QUAL true [get_debug_cores u_ila_3]
set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_3]
set_property C_TRIGIN_EN false [get_debug_cores u_ila_3]
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_3]
set_property port_width 1 [get_debug_ports u_ila_3/clk]
connect_debug_port u_ila_3/clk [get_nets [list mt9d111_pclk_IBUF_BUFG]]
set_property port_width 24 [get_debug_ports u_ila_3/probe0]
connect_debug_port u_ila_3/probe0 [get_nets [list {CamD_VDMA_i/mt9d111_inf_axi_stream_0_m_axis_TDATA[0]} {CamD_VDMA_i/mt9d111_inf_axi_stream_0_m_axis_TDATA[1]} {CamD_VDMA_i/mt9d111_inf_axi_stream_0_m_axis_TDATA[2]} {CamD_VDMA_i/mt9d111_inf_axi_stream_0_m_axis_TDATA[3]} {CamD_VDMA_i/mt9d111_inf_axi_stream_0_m_axis_TDATA[4]} {CamD_VDMA_i/mt9d111_inf_axi_stream_0_m_axis_TDATA[5]} {CamD_VDMA_i/mt9d111_inf_axi_stream_0_m_axis_TDATA[6]} {CamD_VDMA_i/mt9d111_inf_axi_stream_0_m_axis_TDATA[7]} {CamD_VDMA_i/mt9d111_inf_axi_stream_0_m_axis_TDATA[8]} {CamD_VDMA_i/mt9d111_inf_axi_stream_0_m_axis_TDATA[9]} {CamD_VDMA_i/mt9d111_inf_axi_stream_0_m_axis_TDATA[10]} {CamD_VDMA_i/mt9d111_inf_axi_stream_0_m_axis_TDATA[11]} {CamD_VDMA_i/mt9d111_inf_axi_stream_0_m_axis_TDATA[12]} {CamD_VDMA_i/mt9d111_inf_axi_stream_0_m_axis_TDATA[13]} {CamD_VDMA_i/mt9d111_inf_axi_stream_0_m_axis_TDATA[14]} {CamD_VDMA_i/mt9d111_inf_axi_stream_0_m_axis_TDATA[15]} {CamD_VDMA_i/mt9d111_inf_axi_stream_0_m_axis_TDATA[16]} {CamD_VDMA_i/mt9d111_inf_axi_stream_0_m_axis_TDATA[17]} {CamD_VDMA_i/mt9d111_inf_axi_stream_0_m_axis_TDATA[18]} {CamD_VDMA_i/mt9d111_inf_axi_stream_0_m_axis_TDATA[19]} {CamD_VDMA_i/mt9d111_inf_axi_stream_0_m_axis_TDATA[20]} {CamD_VDMA_i/mt9d111_inf_axi_stream_0_m_axis_TDATA[21]} {CamD_VDMA_i/mt9d111_inf_axi_stream_0_m_axis_TDATA[22]} {CamD_VDMA_i/mt9d111_inf_axi_stream_0_m_axis_TDATA[23]}]]
create_debug_port u_ila_0 probe
set_property port_width 3 [get_debug_ports u_ila_0/probe1]
connect_debug_port u_ila_0/probe1 [get_nets [list {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_ARPROT[0]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_ARPROT[1]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_ARPROT[2]}]]
create_debug_port u_ila_0 probe
set_property port_width 4 [get_debug_ports u_ila_0/probe2]
connect_debug_port u_ila_0/probe2 [get_nets [list {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_AWCACHE[0]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_AWCACHE[1]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_AWCACHE[2]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_AWCACHE[3]}]]
create_debug_port u_ila_0 probe
set_property port_width 3 [get_debug_ports u_ila_0/probe3]
connect_debug_port u_ila_0/probe3 [get_nets [list {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_AWPROT[0]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_AWPROT[1]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_AWPROT[2]}]]
create_debug_port u_ila_0 probe
set_property port_width 2 [get_debug_ports u_ila_0/probe4]
connect_debug_port u_ila_0/probe4 [get_nets [list {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_BRESP[0]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_BRESP[1]}]]
create_debug_port u_ila_0 probe
set_property port_width 2 [get_debug_ports u_ila_0/probe5]
connect_debug_port u_ila_0/probe5 [get_nets [list {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_RRESP[0]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_RRESP[1]}]]
create_debug_port u_ila_1 probe
set_property port_width 2 [get_debug_ports u_ila_1/probe1]
connect_debug_port u_ila_1/probe1 [get_nets [list {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_ARBURST[0]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_ARBURST[1]}]]
create_debug_port u_ila_1 probe
set_property port_width 8 [get_debug_ports u_ila_1/probe2]
connect_debug_port u_ila_1/probe2 [get_nets [list {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_ARLEN[0]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_ARLEN[1]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_ARLEN[2]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_ARLEN[3]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_ARLEN[4]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_ARLEN[5]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_ARLEN[6]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_ARLEN[7]}]]
create_debug_port u_ila_1 probe
set_property port_width 3 [get_debug_ports u_ila_1/probe3]
connect_debug_port u_ila_1/probe3 [get_nets [list {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_ARSIZE[0]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_ARSIZE[1]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_ARSIZE[2]}]]
create_debug_port u_ila_1 probe
set_property port_width 64 [get_debug_ports u_ila_1/probe4]
connect_debug_port u_ila_1/probe4 [get_nets [list {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[0]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[1]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[2]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[3]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[4]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[5]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[6]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[7]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[8]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[9]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[10]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[11]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[12]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[13]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[14]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[15]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[16]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[17]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[18]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[19]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[20]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[21]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[22]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[23]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[24]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[25]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[26]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[27]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[28]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[29]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[30]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[31]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[32]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[33]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[34]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[35]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[36]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[37]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[38]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[39]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[40]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[41]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[42]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[43]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[44]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[45]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[46]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[47]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[48]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[49]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[50]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[51]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[52]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[53]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[54]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[55]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[56]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[57]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[58]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[59]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[60]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[61]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[62]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RDATA[63]}]]
create_debug_port u_ila_1 probe
set_property port_width 2 [get_debug_ports u_ila_1/probe5]
connect_debug_port u_ila_1/probe5 [get_nets [list {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RRESP[0]} {CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RRESP[1]}]]
create_debug_port u_ila_1 probe
set_property port_width 32 [get_debug_ports u_ila_1/probe6]
connect_debug_port u_ila_1/probe6 [get_nets [list {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_AWADDR[0]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_AWADDR[1]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_AWADDR[2]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_AWADDR[3]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_AWADDR[4]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_AWADDR[5]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_AWADDR[6]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_AWADDR[7]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_AWADDR[8]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_AWADDR[9]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_AWADDR[10]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_AWADDR[11]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_AWADDR[12]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_AWADDR[13]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_AWADDR[14]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_AWADDR[15]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_AWADDR[16]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_AWADDR[17]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_AWADDR[18]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_AWADDR[19]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_AWADDR[20]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_AWADDR[21]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_AWADDR[22]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_AWADDR[23]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_AWADDR[24]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_AWADDR[25]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_AWADDR[26]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_AWADDR[27]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_AWADDR[28]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_AWADDR[29]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_AWADDR[30]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_AWADDR[31]}]]
create_debug_port u_ila_1 probe
set_property port_width 2 [get_debug_ports u_ila_1/probe7]
connect_debug_port u_ila_1/probe7 [get_nets [list {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_AWBURST[0]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_AWBURST[1]}]]
create_debug_port u_ila_1 probe
set_property port_width 8 [get_debug_ports u_ila_1/probe8]
connect_debug_port u_ila_1/probe8 [get_nets [list {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_AWLEN[0]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_AWLEN[1]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_AWLEN[2]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_AWLEN[3]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_AWLEN[4]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_AWLEN[5]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_AWLEN[6]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_AWLEN[7]}]]
create_debug_port u_ila_1 probe
set_property port_width 3 [get_debug_ports u_ila_1/probe9]
connect_debug_port u_ila_1/probe9 [get_nets [list {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_AWSIZE[0]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_AWSIZE[1]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_AWSIZE[2]}]]
create_debug_port u_ila_1 probe
set_property port_width 2 [get_debug_ports u_ila_1/probe10]
connect_debug_port u_ila_1/probe10 [get_nets [list {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_BRESP[0]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_BRESP[1]}]]
create_debug_port u_ila_1 probe
set_property port_width 32 [get_debug_ports u_ila_1/probe11]
connect_debug_port u_ila_1/probe11 [get_nets [list {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_WDATA[0]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_WDATA[1]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_WDATA[2]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_WDATA[3]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_WDATA[4]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_WDATA[5]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_WDATA[6]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_WDATA[7]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_WDATA[8]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_WDATA[9]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_WDATA[10]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_WDATA[11]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_WDATA[12]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_WDATA[13]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_WDATA[14]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_WDATA[15]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_WDATA[16]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_WDATA[17]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_WDATA[18]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_WDATA[19]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_WDATA[20]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_WDATA[21]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_WDATA[22]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_WDATA[23]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_WDATA[24]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_WDATA[25]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_WDATA[26]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_WDATA[27]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_WDATA[28]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_WDATA[29]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_WDATA[30]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_WDATA[31]}]]
create_debug_port u_ila_1 probe
set_property port_width 4 [get_debug_ports u_ila_1/probe12]
connect_debug_port u_ila_1/probe12 [get_nets [list {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_WSTRB[0]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_WSTRB[1]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_WSTRB[2]} {CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_WSTRB[3]}]]
create_debug_port u_ila_1 probe
set_property port_width 9 [get_debug_ports u_ila_1/probe13]
connect_debug_port u_ila_1/probe13 [get_nets [list {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_AWADDR[0]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_AWADDR[1]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_AWADDR[2]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_AWADDR[3]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_AWADDR[4]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_AWADDR[5]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_AWADDR[6]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_AWADDR[7]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_AWADDR[8]}]]
create_debug_port u_ila_1 probe
set_property port_width 32 [get_debug_ports u_ila_1/probe14]
connect_debug_port u_ila_1/probe14 [get_nets [list {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_WDATA[0]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_WDATA[1]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_WDATA[2]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_WDATA[3]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_WDATA[4]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_WDATA[5]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_WDATA[6]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_WDATA[7]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_WDATA[8]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_WDATA[9]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_WDATA[10]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_WDATA[11]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_WDATA[12]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_WDATA[13]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_WDATA[14]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_WDATA[15]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_WDATA[16]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_WDATA[17]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_WDATA[18]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_WDATA[19]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_WDATA[20]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_WDATA[21]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_WDATA[22]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_WDATA[23]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_WDATA[24]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_WDATA[25]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_WDATA[26]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_WDATA[27]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_WDATA[28]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_WDATA[29]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_WDATA[30]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_WDATA[31]}]]
create_debug_port u_ila_1 probe
set_property port_width 9 [get_debug_ports u_ila_1/probe15]
connect_debug_port u_ila_1/probe15 [get_nets [list {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_ARADDR[0]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_ARADDR[1]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_ARADDR[2]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_ARADDR[3]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_ARADDR[4]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_ARADDR[5]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_ARADDR[6]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_ARADDR[7]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_ARADDR[8]}]]
create_debug_port u_ila_1 probe
set_property port_width 32 [get_debug_ports u_ila_1/probe16]
connect_debug_port u_ila_1/probe16 [get_nets [list {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_RDATA[0]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_RDATA[1]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_RDATA[2]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_RDATA[3]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_RDATA[4]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_RDATA[5]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_RDATA[6]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_RDATA[7]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_RDATA[8]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_RDATA[9]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_RDATA[10]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_RDATA[11]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_RDATA[12]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_RDATA[13]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_RDATA[14]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_RDATA[15]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_RDATA[16]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_RDATA[17]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_RDATA[18]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_RDATA[19]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_RDATA[20]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_RDATA[21]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_RDATA[22]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_RDATA[23]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_RDATA[24]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_RDATA[25]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_RDATA[26]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_RDATA[27]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_RDATA[28]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_RDATA[29]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_RDATA[30]} {CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_RDATA[31]}]]
create_debug_port u_ila_1 probe
set_property port_width 1 [get_debug_ports u_ila_1/probe17]
connect_debug_port u_ila_1/probe17 [get_nets [list CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_ARREADY]]
create_debug_port u_ila_1 probe
set_property port_width 1 [get_debug_ports u_ila_1/probe18]
connect_debug_port u_ila_1/probe18 [get_nets [list CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_ARVALID]]
create_debug_port u_ila_1 probe
set_property port_width 1 [get_debug_ports u_ila_1/probe19]
connect_debug_port u_ila_1/probe19 [get_nets [list CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RLAST]]
create_debug_port u_ila_1 probe
set_property port_width 1 [get_debug_ports u_ila_1/probe20]
connect_debug_port u_ila_1/probe20 [get_nets [list CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RREADY]]
create_debug_port u_ila_1 probe
set_property port_width 1 [get_debug_ports u_ila_1/probe21]
connect_debug_port u_ila_1/probe21 [get_nets [list CamD_VDMA_i/axi_vdma_0_M_AXI_MM2S_RVALID]]
create_debug_port u_ila_1 probe
set_property port_width 1 [get_debug_ports u_ila_1/probe22]
connect_debug_port u_ila_1/probe22 [get_nets [list CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_AWREADY]]
create_debug_port u_ila_1 probe
set_property port_width 1 [get_debug_ports u_ila_1/probe23]
connect_debug_port u_ila_1/probe23 [get_nets [list CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_AWVALID]]
create_debug_port u_ila_1 probe
set_property port_width 1 [get_debug_ports u_ila_1/probe24]
connect_debug_port u_ila_1/probe24 [get_nets [list CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_BREADY]]
create_debug_port u_ila_1 probe
set_property port_width 1 [get_debug_ports u_ila_1/probe25]
connect_debug_port u_ila_1/probe25 [get_nets [list CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_BVALID]]
create_debug_port u_ila_1 probe
set_property port_width 1 [get_debug_ports u_ila_1/probe26]
connect_debug_port u_ila_1/probe26 [get_nets [list CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_WLAST]]
create_debug_port u_ila_1 probe
set_property port_width 1 [get_debug_ports u_ila_1/probe27]
connect_debug_port u_ila_1/probe27 [get_nets [list CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_WREADY]]
create_debug_port u_ila_1 probe
set_property port_width 1 [get_debug_ports u_ila_1/probe28]
connect_debug_port u_ila_1/probe28 [get_nets [list CamD_VDMA_i/axi_vdma_0_M_AXI_S2MM_WVALID]]
create_debug_port u_ila_1 probe
set_property port_width 1 [get_debug_ports u_ila_1/probe29]
connect_debug_port u_ila_1/probe29 [get_nets [list CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_ARREADY]]
create_debug_port u_ila_1 probe
set_property port_width 1 [get_debug_ports u_ila_1/probe30]
connect_debug_port u_ila_1/probe30 [get_nets [list CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_ARVALID]]
create_debug_port u_ila_1 probe
set_property port_width 1 [get_debug_ports u_ila_1/probe31]
connect_debug_port u_ila_1/probe31 [get_nets [list CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_AWREADY]]
create_debug_port u_ila_1 probe
set_property port_width 1 [get_debug_ports u_ila_1/probe32]
connect_debug_port u_ila_1/probe32 [get_nets [list CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_AWVALID]]
create_debug_port u_ila_1 probe
set_property port_width 1 [get_debug_ports u_ila_1/probe33]
connect_debug_port u_ila_1/probe33 [get_nets [list CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_BREADY]]
create_debug_port u_ila_1 probe
set_property port_width 1 [get_debug_ports u_ila_1/probe34]
connect_debug_port u_ila_1/probe34 [get_nets [list CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_BVALID]]
create_debug_port u_ila_1 probe
set_property port_width 1 [get_debug_ports u_ila_1/probe35]
connect_debug_port u_ila_1/probe35 [get_nets [list CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_RREADY]]
create_debug_port u_ila_1 probe
set_property port_width 1 [get_debug_ports u_ila_1/probe36]
connect_debug_port u_ila_1/probe36 [get_nets [list CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_RVALID]]
create_debug_port u_ila_1 probe
set_property port_width 1 [get_debug_ports u_ila_1/probe37]
connect_debug_port u_ila_1/probe37 [get_nets [list CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_WREADY]]
create_debug_port u_ila_1 probe
set_property port_width 1 [get_debug_ports u_ila_1/probe38]
connect_debug_port u_ila_1/probe38 [get_nets [list CamD_VDMA_i/processing_system7_0_axi_periph_M00_AXI_WVALID]]
create_debug_port u_ila_2 probe
set_property port_width 1 [get_debug_ports u_ila_2/probe1]
connect_debug_port u_ila_2/probe1 [get_nets [list CamD_VDMA_i/axi_vdma_0_M_AXIS_MM2S_TLAST]]
create_debug_port u_ila_2 probe
set_property port_width 1 [get_debug_ports u_ila_2/probe2]
connect_debug_port u_ila_2/probe2 [get_nets [list CamD_VDMA_i/axi_vdma_0_M_AXIS_MM2S_TREADY]]
create_debug_port u_ila_2 probe
set_property port_width 1 [get_debug_ports u_ila_2/probe3]
connect_debug_port u_ila_2/probe3 [get_nets [list CamD_VDMA_i/axi_vdma_0_M_AXIS_MM2S_TUSER]]
create_debug_port u_ila_2 probe
set_property port_width 1 [get_debug_ports u_ila_2/probe4]
connect_debug_port u_ila_2/probe4 [get_nets [list CamD_VDMA_i/axi_vdma_0_M_AXIS_MM2S_TVALID]]
create_debug_port u_ila_2 probe
set_property port_width 1 [get_debug_ports u_ila_2/probe5]
connect_debug_port u_ila_2/probe5 [get_nets [list CamD_VDMA_i/custom_vtc_0_vtg_sync]]
create_debug_port u_ila_3 probe
set_property port_width 1 [get_debug_ports u_ila_3/probe1]
connect_debug_port u_ila_3/probe1 [get_nets [list CamD_VDMA_i/mt9d111_inf_axi_stream_0_m_axis_TLAST]]
create_debug_port u_ila_3 probe
set_property port_width 1 [get_debug_ports u_ila_3/probe2]
connect_debug_port u_ila_3/probe2 [get_nets [list CamD_VDMA_i/mt9d111_inf_axi_stream_0_m_axis_TREADY]]
create_debug_port u_ila_3 probe
set_property port_width 1 [get_debug_ports u_ila_3/probe3]
connect_debug_port u_ila_3/probe3 [get_nets [list CamD_VDMA_i/mt9d111_inf_axi_stream_0_m_axis_TVALID]]
create_debug_port u_ila_3 probe
set_property port_width 1 [get_debug_ports u_ila_3/probe4]
connect_debug_port u_ila_3/probe4 [get_nets [list CamD_VDMA_i/mt9d111_inf_axi_stream_0_s2mm_fsync]]
set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]


次にハードウェアをエクスポートして、SDKを立ち上げる。

必ず Sourcesウインドウから、CamD_VDMA_i(IP Integrator の Diagramファイル)を開いてから、CamD_VDMA_i を右クリックし、右クリックメニューから Export Hardware for SDK... を選択した。
Cam_VDMA_174_140129.png

・Export Hardware for SDKダイアログが表示された。Launch SDKにチェックを入れて、OKボタンをクリックした。
Cam_VDMA_175_140129.png

・SDKが立ち上がった。
Cam_VDMA_177_140129.png

Vivado 2013.4でAXI VDMAを使ったカメラ表示回路の作製15(ハードウェアのデバック3)”に続く。
  1. 2014年01月31日 04:32 |
  2. Vivado
  3. | トラックバック:0
  4. | コメント:0

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