FC2カウンター FPGAの部屋 AXI VDMAを使ったカメラ画像回路の作製1(プロジェクトの作製)
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FPGAやCPLDの話題やFPGA用のツールの話題などです。 マニアックです。 日記も書きます。

FPGAの部屋

FPGAの部屋の有用と思われるコンテンツのまとめサイトを作りました。Xilinx ISEの初心者の方には、FPGAリテラシーおよびチュートリアルのページをお勧めいたします。

AXI VDMAを使ったカメラ画像回路の作製1(プロジェクトの作製)

Vivado 2013.4でAXI VDMAを使ったカメラ表示回路の作製17(ハードウェアのデバック5)”まで、Vivado 2013.4でAXI VDMA を使ったカメラ画像回路を作ってきたが、Vivado 2013.4だと、動作が重いので、ISEで試作してみようと思った。Vivado 2013.4は私の家の古いパソコンではとっても重い。

まずは、Project Navigator の ZedBoard用のプロジェクトを作製した。
Cam_VDMA_ISE_1_140217.png

次に、XPSプロジェクトを下に示す。
Cam_VDMA_ISE_2_140217.png

Cam_VDMA_ISE_3_140217.png

Cam_VDMA_ISE_4_140217.png

AXI_GP0、AXI_HP0 のクロックは 100MHz だ。

下に、system_top.ucf を示す。

NET "vga_blue[0]" LOC = Y21;
NET "vga_blue[1]" LOC = Y20;
NET "vga_blue[2]" LOC = AB20;
NET "vga_blue[3]" LOC = AB19;
NET "vga_blue[0]" IOSTANDARD = LVCMOS33;
NET "vga_blue[1]" IOSTANDARD = LVCMOS33;
NET "vga_blue[2]" IOSTANDARD = LVCMOS33;
NET "vga_blue[3]" IOSTANDARD = LVCMOS33;
INST "vga_blue_0_OBUF" IOB =FORCE;
INST "vga_blue_1_OBUF" IOB =FORCE;
INST "vga_blue_2_OBUF" IOB =FORCE;
INST "vga_blue_3_OBUF" IOB =FORCE;
NET "vga_green[0]" LOC = AB22;
NET "vga_green[1]" LOC = AA22;
NET "vga_green[2]" LOC = AB21;
NET "vga_green[3]" LOC = AA21;
NET "vga_green[0]" IOSTANDARD = LVCMOS33;
NET "vga_green[1]" IOSTANDARD = LVCMOS33;
NET "vga_green[2]" IOSTANDARD = LVCMOS33;
NET "vga_green[3]" IOSTANDARD = LVCMOS33;
INST "vga_green_0_OBUF" IOB =FORCE;
INST "vga_green_1_OBUF" IOB =FORCE;
INST "vga_green_2_OBUF" IOB =FORCE;
INST "vga_green_3_OBUF" IOB =FORCE;
NET "vga_red[0]" LOC = V20;
NET "vga_red[1]" LOC = U20;
NET "vga_red[2]" LOC = V19;
NET "vga_red[3]" LOC = V18;
NET "vga_red[0]" IOSTANDARD = LVCMOS33;
NET "vga_red[1]" IOSTANDARD = LVCMOS33;
NET "vga_red[2]" IOSTANDARD = LVCMOS33;
NET "vga_red[3]" IOSTANDARD = LVCMOS33;
INST "vga_red_0_OBUF" IOB =FORCE;
INST "vga_red_1_OBUF" IOB =FORCE;
INST "vga_red_2_OBUF" IOB =FORCE;
INST "vga_red_3_OBUF" IOB =FORCE;
NET "vga_hsync" LOC = AA19;
NET "vga_vsync" LOC = Y19;
NET "vga_hsync" IOSTANDARD = LVCMOS33;
NET "vga_vsync" IOSTANDARD = LVCMOS33;
INST "vga_hsync_OBUF" IOB =FORCE;
INST "vga_vsync_OBUF" IOB =FORCE;

INST "hdmi_clk_OBUF" IOB =FORCE;
NET "hdmi_clk" LOC = W18;
NET "hdmi_clk" IOSTANDARD = LVCMOS33;
INST "hdmi_vsync_OBUF" IOB =FORCE;
NET "hdmi_vsync" LOC = W17;
NET "hdmi_vsync" IOSTANDARD = LVCMOS33;
INST "hdmi_hsync_OBUF" IOB =FORCE;
NET "hdmi_hsync" LOC = V17;
NET "hdmi_hsync" IOSTANDARD = LVCMOS33;
INST "hdmi_data_e_OBUF" IOB =FORCE;
NET "hdmi_data_e" LOC = U16;
NET "hdmi_data_e" IOSTANDARD = LVCMOS33;
INST "hdmi_data_0_OBUF" IOB =FORCE;
NET "hdmi_data[0]" LOC = Y13;
NET "hdmi_data[0]" IOSTANDARD = LVCMOS33;
INST "hdmi_data_1_OBUF" IOB =FORCE;
NET "hdmi_data[1]" LOC = AA13;
NET "hdmi_data[1]" IOSTANDARD = LVCMOS33;
INST "hdmi_data_2_OBUF" IOB =FORCE;
NET "hdmi_data[2]" LOC = AA14;
NET "hdmi_data[2]" IOSTANDARD = LVCMOS33;
INST "hdmi_data_3_OBUF" IOB =FORCE;
NET "hdmi_data[3]" LOC = Y14;
NET "hdmi_data[3]" IOSTANDARD = LVCMOS33;
INST "hdmi_data_4_OBUF" IOB =FORCE;
NET "hdmi_data[4]" LOC = AB15;
NET "hdmi_data[4]" IOSTANDARD = LVCMOS33;
INST "hdmi_data_5_OBUF" IOB =FORCE;
NET "hdmi_data[5]" LOC = AB16;
NET "hdmi_data[5]" IOSTANDARD = LVCMOS33;
INST "hdmi_data_6_OBUF" IOB =FORCE;
NET "hdmi_data[6]" LOC = AA16;
NET "hdmi_data[6]" IOSTANDARD = LVCMOS33;
INST "hdmi_data_7_OBUF" IOB =FORCE;
NET "hdmi_data[7]" LOC = AB17;
NET "hdmi_data[7]" IOSTANDARD = LVCMOS33;
INST "hdmi_data_8_OBUF" IOB =FORCE;
NET "hdmi_data[8]" LOC = AA17;
NET "hdmi_data[8]" IOSTANDARD = LVCMOS33;
INST "hdmi_data_9_OBUF" IOB =FORCE;
NET "hdmi_data[9]" LOC = Y15;
NET "hdmi_data[9]" IOSTANDARD = LVCMOS33;
INST "hdmi_data_10_OBUF" IOB =FORCE;
NET "hdmi_data[10]" LOC = W13;
NET "hdmi_data[10]" IOSTANDARD = LVCMOS33;
INST "hdmi_data_11_OBUF" IOB =FORCE;
NET "hdmi_data[11]" LOC = W15;
NET "hdmi_data[11]" IOSTANDARD = LVCMOS33;
INST "hdmi_data_12_OBUF" IOB =FORCE;
NET "hdmi_data[12]" LOC = V15;
NET "hdmi_data[12]" IOSTANDARD = LVCMOS33;
INST "hdmi_data_13_OBUF" IOB =FORCE;
NET "hdmi_data[13]" LOC = U17;
NET "hdmi_data[13]" IOSTANDARD = LVCMOS33;
INST "hdmi_data_14_OBUF" IOB =FORCE;
NET "hdmi_data[14]" LOC = V14;
NET "hdmi_data[14]" IOSTANDARD = LVCMOS33;
INST "hdmi_data_15_OBUF" IOB =FORCE;
NET "hdmi_data[15]" LOC = V13;
NET "hdmi_data[15]" IOSTANDARD = LVCMOS33;
NET "hdmi_iic_Scl" LOC = AA18;
NET "hdmi_iic_Scl" IOSTANDARD = LVCMOS33;
NET "hdmi_iic_Sda" LOC = Y16;
NET "hdmi_iic_Sda" IOSTANDARD = LVCMOS33;
NET "hdmi_data[15]" SLEW = FAST;
NET "hdmi_data[14]" SLEW = FAST;
NET "hdmi_data[13]" SLEW = FAST;
NET "hdmi_data[12]" SLEW = FAST;
NET "hdmi_data[11]" SLEW = FAST;
NET "hdmi_data[10]" SLEW = FAST;
NET "hdmi_data[9]" SLEW = FAST;
NET "hdmi_data[8]" SLEW = FAST;
NET "hdmi_data[7]" SLEW = FAST;
NET "hdmi_data[6]" SLEW = FAST;
NET "hdmi_data[5]" SLEW = FAST;
NET "hdmi_data[4]" SLEW = FAST;
NET "hdmi_data[3]" SLEW = FAST;
NET "hdmi_data[2]" SLEW = FAST;
NET "hdmi_data[1]" SLEW = FAST;
NET "hdmi_data[0]" SLEW = FAST;
NET "vga_blue[3]" SLEW = FAST;
NET "vga_blue[2]" SLEW = FAST;
NET "vga_blue[1]" SLEW = FAST;
NET "vga_blue[0]" SLEW = FAST;
NET "vga_green[3]" SLEW = FAST;
NET "vga_green[2]" SLEW = FAST;
NET "vga_green[1]" SLEW = FAST;
NET "vga_green[0]" SLEW = FAST;
NET "vga_red[3]" SLEW = FAST;
NET "vga_red[2]" SLEW = FAST;
NET "vga_red[1]" SLEW = FAST;
NET "vga_red[0]" SLEW = FAST;
NET "hdmi_clk" SLEW = FAST;
NET "hdmi_data_e" SLEW = FAST;
NET "hdmi_hsync" SLEW = FAST;
NET "hdmi_iic_Scl" SLEW = SLOW;
NET "hdmi_vsync" SLEW = FAST;
NET "vga_hsync" SLEW = FAST;
NET "vga_vsync" SLEW = FAST;
NET "mt9d111_d[7]" LOC = W12;
NET "mt9d111_d[6]" LOC = V12;
NET "mt9d111_d[5]" LOC = W11;
NET "mt9d111_d[4]" LOC = W10;
NET "mt9d111_d[3]" LOC = V10;
NET "mt9d111_d[2]" LOC = V9;
NET "mt9d111_d[1]" LOC = W8;
NET "mt9d111_d[0]" LOC = V8;
NET "mt9d111_d[7]" IOSTANDARD = LVCMOS33;
NET "mt9d111_d[6]" IOSTANDARD = LVCMOS33;
NET "mt9d111_d[5]" IOSTANDARD = LVCMOS33;
NET "mt9d111_d[4]" IOSTANDARD = LVCMOS33;
NET "mt9d111_d[3]" IOSTANDARD = LVCMOS33;
NET "mt9d111_d[2]" IOSTANDARD = LVCMOS33;
NET "mt9d111_d[1]" IOSTANDARD = LVCMOS33;
NET "mt9d111_d[0]" IOSTANDARD = LVCMOS33;
NET "mt9d111_href" LOC = AB10;
NET "mt9d111_pclk" LOC = AA9;
NET "mt9d111_Scl" LOC = Y11;
NET "mt9d111_Sda" LOC = AB11;
NET "mt9d111_standby" LOC = Y10;
NET "mt9d111_vsync" LOC = AA11;
NET "mt9d111_xck" LOC = AA8;
NET "mt9d111_href" IOSTANDARD = LVCMOS33;
NET "mt9d111_pclk" IOSTANDARD = LVCMOS33;
NET "mt9d111_Scl" IOSTANDARD = LVCMOS33;
NET "mt9d111_Sda" IOSTANDARD = LVCMOS33;
NET "mt9d111_standby" IOSTANDARD = LVCMOS33;
NET "mt9d111_vsync" IOSTANDARD = LVCMOS33;
NET "mt9d111_xck" IOSTANDARD = LVTTL;
NET "mt9d111_d[0]" OFFSET = IN 10.8 ns VALID 21.7 ns BEFORE "mt9d111_pclk" RISING;
NET "mt9d111_d[1]" OFFSET = IN 10.8 ns VALID 21.7 ns BEFORE "mt9d111_pclk" RISING;
NET "mt9d111_d[2]" OFFSET = IN 10.8 ns VALID 21.7 ns BEFORE "mt9d111_pclk" RISING;
NET "mt9d111_d[3]" OFFSET = IN 10.8 ns VALID 21.7 ns BEFORE "mt9d111_pclk" RISING;
NET "mt9d111_d[4]" OFFSET = IN 10.8 ns VALID 21.7 ns BEFORE "mt9d111_pclk" RISING;
NET "mt9d111_d[5]" OFFSET = IN 10.8 ns VALID 21.7 ns BEFORE "mt9d111_pclk" RISING;
NET "mt9d111_d[6]" OFFSET = IN 10.8 ns VALID 21.7 ns BEFORE "mt9d111_pclk" RISING;
NET "mt9d111_d[7]" OFFSET = IN 10.8 ns VALID 21.7 ns BEFORE "mt9d111_pclk" RISING;
NET "mt9d111_href" OFFSET = IN 10.8 ns VALID 21.7 ns BEFORE "mt9d111_pclk" RISING;
NET "mt9d111_vsync" OFFSET = IN 10.8 ns VALID 21.7 ns BEFORE "mt9d111_pclk" RISING;
NET "mt9d111_Scl" PULLUP;
NET "mt9d111_Sda" PULLUP;


現在、論理合成中だ。

”AXI VDMAを使ったカメラ画像回路の作製2(Xilinxアンサーを検索)”に続く。
  1. 2014年02月17日 04:42 |
  2. ZedBoard
  3. | トラックバック:0
  4. | コメント:0

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