Vivado HLS 2014.1でラプラシアン・フィルタ関数をaxi masterモジュールにする６（パイプライン化ソースを実機テスト１）

”Vivado HLS 2014.1でラプラシアン・フィルタ関数をaxi masterモジュールにする５（Cソースのフィルタ処理をパイプライン化）”の続き。

前回は、twitter で tu1978 さんに頂いたフィルタ処理をパイプライン化したラプラシアンフィルタのCソースを合成した。今日は、XPS用のIPを生成して実機テストしてみる。

・最初に、Vivado HLS 2014.1 で、合成後のたフィルタ処理をパイプライン化したラプラシアンフィルタのCソースをXPS用にIPを行った。

・XPSのIP、lap_filter_axim_top_v1_00_a を、以前から使用している Zed_OOB_Desin2_HLS_147 という名前のProject Navigator プロジェクトの中のXPSプロジェクト(system) の pcores フォルダにコピーした。


・XPSを立ちあげて、Project メニュー　-> Clean All Generate Files を行った。


・Project Navigator で、左下のProcesses ウインドウの Generate Programming File をダブルクリックして、論理合成、インプリメント、ビットストリームの生成を行った。


・ビットストリームの生成まで終了したが、Timing Constrains のエラーが出ていた。


・Processes ウインドウのImplement Desgin -> Place & Route -> Generate Post-Place & Route Static Timing -> Analyze Post-Place & Route Static Timing をダブルクリックして、静的タイミング解析結果を表示した。


lap_filter_axim_top_0 つまり、Vivado HLS 2014.1 で作ったIPのFF間でタイミング・エラーが発生している。
最初のタイミング・エラーの情報を下に引用する。

 ================================================================================ 
 Timing constraint: TS_clk_fpga_0 = PERIOD TIMEGRP "clk_fpga_0" 100 MHz HIGH 50%; 
 For more information, see Period Analysis in the Timing Closure User Guide (UG612). 
  3814414 paths analyzed, 74771 endpoints analyzed, 43 failing endpoints 
  43 timing errors detected. (43 setup errors, 0 hold errors, 0 component switching limit errors) 
  Minimum period is  10.631ns. 
 -------------------------------------------------------------------------------- 
  
 Paths for end point system_i/lap_filter_axim_top_0/lap_filter_axim_top_0/lap_filter_axim_U/grp_filter_line_fu_397/tmp_i_37_reg_859_9 (SLICE_X82Y21.CIN), 244131 paths 
 -------------------------------------------------------------------------------- 
 Slack (setup path):     -0.631ns (requirement - (data path - clock path skew + uncertainty)) 
   Source:               system_i/lap_filter_axim_top_0/lap_filter_axim_top_0/lap_filter_axim_U/grp_filter_line_fu_397/ap_reg_ppstg_exitcond_reg_804_pp0_it3_0 (FF) 
   Destination:          system_i/lap_filter_axim_top_0/lap_filter_axim_top_0/lap_filter_axim_U/grp_filter_line_fu_397/tmp_i_37_reg_859_9 (FF) 
   Requirement:          10.000ns 
   Data Path Delay:      10.564ns (Levels of Logic = 13) 
   Clock Path Skew:      -0.032ns (0.158 - 0.190) 
   Source Clock:         system_i/processing_system7_0_FCLK_CLK0 rising at 0.000ns 
   Destination Clock:    system_i/processing_system7_0_FCLK_CLK0 rising at 10.000ns 
   Clock Uncertainty:    0.035ns 
  
   Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE 
     Total System Jitter (TSJ):  0.070ns 
     Total Input Jitter (TIJ):   0.000ns 
     Discrete Jitter (DJ):       0.000ns 
     Phase Error (PE):           0.000ns 
  
   Maximum Data Path at Slow Process Corner: system_i/lap_filter_axim_top_0/lap_filter_axim_top_0/lap_filter_axim_U/grp_filter_line_fu_397/ap_reg_ppstg_exitcond_reg_804_pp0_it3_0 to system_i/lap_filter_axim_top_0/lap_filter_axim_top_0/lap_filter_axim_U/grp_filter_line_fu_397/tmp_i_37_reg_859_9 
     Location             Delay type         Delay(ns)  Physical Resource 
                                                        Logical Resource(s) 
     -------------------------------------------------  ------------------- 
     SLICE_X83Y14.CQ      Tcko                  0.456   system_i/lap_filter_axim_top_0/lap_filter_axim_top_0/lap_filter_axim_U/grp_filter_line_fu_397/ap_reg_ppstg_exitcond_reg_804_pp0_it3_0 
                                                        system_i/lap_filter_axim_top_0/lap_filter_axim_top_0/lap_filter_axim_U/grp_filter_line_fu_397/ap_reg_ppstg_exitcond_reg_804_pp0_it3_0 
     SLICE_X81Y14.C3      net (fanout=4)        0.673   system_i/lap_filter_axim_top_0/lap_filter_axim_top_0/lap_filter_axim_U/grp_filter_line_fu_397/ap_reg_ppstg_exitcond_reg_804_pp0_it3_0 
     SLICE_X81Y14.C       Tilo                  0.124   system_i/lap_filter_axim_top_0/lap_filter_axim_top_0/lap_filter_axim_U/grp_filter_line_fu_397/current_2_V_1_fu_84<7> 
                                                        system_i/lap_filter_axim_top_0/lap_filter_axim_top_0/lap_filter_axim_U/grp_filter_line_fu_397/Mmux_current_2_V_phi_fu_247_p41101_1 
     SLICE_X81Y14.D4      net (fanout=6)        0.458   system_i/lap_filter_axim_top_0/lap_filter_axim_top_0/lap_filter_axim_U/grp_filter_line_fu_397/Mmux_current_2_V_phi_fu_247_p41101 
     SLICE_X81Y14.D       Tilo                  0.124   system_i/lap_filter_axim_top_0/lap_filter_axim_top_0/lap_filter_axim_U/grp_filter_line_fu_397/current_2_V_1_fu_84<7> 
                                                        system_i/lap_filter_axim_top_0/lap_filter_axim_top_0/lap_filter_axim_U/grp_filter_line_fu_397/ADDERTREE_INTERNAL_Madd1_lut<0> 
     SLICE_X80Y15.A5      net (fanout=1)        0.465   system_i/lap_filter_axim_top_0/lap_filter_axim_top_0/lap_filter_axim_U/grp_filter_line_fu_397/ADDERTREE_INTERNAL_Madd1_lut<0> 
     SLICE_X80Y15.COUT    Topcya                0.656   system_i/lap_filter_axim_top_0/lap_filter_axim_top_0/lap_filter_axim_U/grp_filter_line_fu_397/ADDERTREE_INTERNAL_Madd1_cy<3> 
                                                        system_i/lap_filter_axim_top_0/lap_filter_axim_top_0/lap_filter_axim_U/grp_filter_line_fu_397/ADDERTREE_INTERNAL_Madd1_lut<0>_rt 
                                                        system_i/lap_filter_axim_top_0/lap_filter_axim_top_0/lap_filter_axim_U/grp_filter_line_fu_397/ADDERTREE_INTERNAL_Madd1_cy<3> 
     SLICE_X80Y16.CIN     net (fanout=1)        0.000   system_i/lap_filter_axim_top_0/lap_filter_axim_top_0/lap_filter_axim_U/grp_filter_line_fu_397/ADDERTREE_INTERNAL_Madd1_cy<3> 
     SLICE_X80Y16.CMUX    Tcinc                 0.417   system_i/lap_filter_axim_top_0/lap_filter_axim_top_0/lap_filter_axim_U/grp_filter_line_fu_397/ADDERTREE_INTERNAL_Madd_71 
                                                        system_i/lap_filter_axim_top_0/lap_filter_axim_top_0/lap_filter_axim_U/grp_filter_line_fu_397/ADDERTREE_INTERNAL_Madd1_cy<7> 
     SLICE_X81Y18.C4      net (fanout=1)        0.900   system_i/lap_filter_axim_top_0/lap_filter_axim_top_0/lap_filter_axim_U/grp_filter_line_fu_397/ADDERTREE_INTERNAL_Madd_61 
     SLICE_X81Y18.CMUX    Tilo                  0.356   system_i/lap_filter_axim_top_0/lap_filter_axim_top_0/lap_filter_axim_U/grp_filter_line_fu_397/y_reg_869<7> 
                                                        system_i/lap_filter_axim_top_0/lap_filter_axim_top_0/lap_filter_axim_U/grp_filter_line_fu_397/ADDERTREE_INTERNAL_Madd26 
     SLICE_X81Y18.D5      net (fanout=2)        0.422   system_i/lap_filter_axim_top_0/lap_filter_axim_top_0/lap_filter_axim_U/grp_filter_line_fu_397/ADDERTREE_INTERNAL_Madd26 
     SLICE_X81Y18.COUT    Topcyd                0.525   system_i/lap_filter_axim_top_0/lap_filter_axim_top_0/lap_filter_axim_U/grp_filter_line_fu_397/y_reg_869<7> 
                                                        system_i/lap_filter_axim_top_0/lap_filter_axim_top_0/lap_filter_axim_U/grp_filter_line_fu_397/ADDERTREE_INTERNAL_Madd2_lut<0>7 
                                                        system_i/lap_filter_axim_top_0/lap_filter_axim_top_0/lap_filter_axim_U/grp_filter_line_fu_397/ADDERTREE_INTERNAL_Madd2_cy<0>_6 
     SLICE_X81Y19.CIN     net (fanout=1)        0.000   system_i/lap_filter_axim_top_0/lap_filter_axim_top_0/lap_filter_axim_U/grp_filter_line_fu_397/ADDERTREE_INTERNAL_Madd2_cy<0>7 
     SLICE_X81Y19.DMUX    Tcind                 0.495   system_i/lap_filter_axim_top_0/lap_filter_axim_top_0/lap_filter_axim_U/grp_filter_line_fu_397/ADDERTREE_INTERNAL_Madd_102 
                                                        system_i/lap_filter_axim_top_0/lap_filter_axim_top_0/lap_filter_axim_U/grp_filter_line_fu_397/ADDERTREE_INTERNAL_Madd2_xor<0>_10 
     SLICE_X83Y18.C6      net (fanout=33)       0.446   system_i/lap_filter_axim_top_0/lap_filter_axim_top_0/lap_filter_axim_U/grp_filter_line_fu_397/ADDERTREE_INTERNAL_Madd_112 
     SLICE_X83Y18.C       Tilo                  0.124   system_i/lap_filter_axim_top_0/lap_filter_axim_top_0/lap_filter_axim_U/grp_filter_line_fu_397/current_0_V_1_fu_76<3> 
                                                        system_i/lap_filter_axim_top_0/lap_filter_axim_top_0/lap_filter_axim_U/grp_filter_line_fu_397/Mmux_current_0_V_phi_fu_238_p431 
     SLICE_X83Y19.C4      net (fanout=1)        0.571   system_i/lap_filter_axim_top_0/lap_filter_axim_top_0/lap_filter_axim_U/grp_filter_line_fu_397/current_0_V_phi_fu_238_p4<2> 
     SLICE_X83Y19.CMUX    Tilo                  0.356   system_i/lap_filter_axim_top_0/lap_filter_axim_top_0/lap_filter_axim_U/grp_filter_line_fu_397/ADDERTREE_INTERNAL_Madd_36 
                                                        system_i/lap_filter_axim_top_0/lap_filter_axim_top_0/lap_filter_axim_U/grp_filter_line_fu_397/ADDERTREE_INTERNAL_Madd62 
     SLICE_X83Y19.DX      net (fanout=2)        0.617   system_i/lap_filter_axim_top_0/lap_filter_axim_top_0/lap_filter_axim_U/grp_filter_line_fu_397/ADDERTREE_INTERNAL_Madd62 
     SLICE_X83Y19.COUT    Tdxcy                 0.385   system_i/lap_filter_axim_top_0/lap_filter_axim_top_0/lap_filter_axim_U/grp_filter_line_fu_397/ADDERTREE_INTERNAL_Madd_36 
                                                        system_i/lap_filter_axim_top_0/lap_filter_axim_top_0/lap_filter_axim_U/grp_filter_line_fu_397/ADDERTREE_INTERNAL_Madd6_cy<0>_2 
     SLICE_X83Y20.CIN     net (fanout=1)        0.000   system_i/lap_filter_axim_top_0/lap_filter_axim_top_0/lap_filter_axim_U/grp_filter_line_fu_397/ADDERTREE_INTERNAL_Madd6_cy<0>3 
     SLICE_X83Y20.BQ      Tito_logic            0.674   system_i/lap_filter_axim_top_0/lap_filter_axim_top_0/lap_filter_axim_U/grp_filter_line_fu_397/ADDERTREE_INTERNAL_Madd_76 
                                                        system_i/lap_filter_axim_top_0/lap_filter_axim_top_0/lap_filter_axim_U/grp_filter_line_fu_397/ADDERTREE_INTERNAL_Madd6_cy<0>_6 
                                                        system_i/lap_filter_axim_top_0/lap_filter_axim_top_0/lap_filter_axim_U/grp_filter_line_fu_397/ADDERTREE_INTERNAL_Madd_56_rt 
     SLICE_X82Y20.B4      net (fanout=1)        0.449   system_i/lap_filter_axim_top_0/lap_filter_axim_top_0/lap_filter_axim_U/grp_filter_line_fu_397/ADDERTREE_INTERNAL_Madd_56 
     SLICE_X82Y20.COUT    Topcyb                0.657   system_i/lap_filter_axim_top_0/lap_filter_axim_top_0/lap_filter_axim_U/grp_filter_line_fu_397/tmp_i_37_reg_859<7> 
                                                        system_i/lap_filter_axim_top_0/lap_filter_axim_top_0/lap_filter_axim_U/grp_filter_line_fu_397/ADDERTREE_INTERNAL_Madd7_lut<5> 
                                                        system_i/lap_filter_axim_top_0/lap_filter_axim_top_0/lap_filter_axim_U/grp_filter_line_fu_397/ADDERTREE_INTERNAL_Madd7_cy<7> 
     SLICE_X82Y21.CIN     net (fanout=1)        0.000   system_i/lap_filter_axim_top_0/lap_filter_axim_top_0/lap_filter_axim_U/grp_filter_line_fu_397/ADDERTREE_INTERNAL_Madd7_cy<7> 
     SLICE_X82Y21.CLK     Tcinck                0.214   system_i/lap_filter_axim_top_0/lap_filter_axim_top_0/lap_filter_axim_U/grp_filter_line_fu_397/tmp_i_37_reg_859<11> 
                                                        system_i/lap_filter_axim_top_0/lap_filter_axim_top_0/lap_filter_axim_U/grp_filter_line_fu_397/ADDERTREE_INTERNAL_Madd7_xor<11> 
                                                        system_i/lap_filter_axim_top_0/lap_filter_axim_top_0/lap_filter_axim_U/grp_filter_line_fu_397/tmp_i_37_reg_859_9 
     -------------------------------------------------  --------------------------- 
     Total                                     10.564ns (5.563ns logic, 5.001ns route) 
                                                        (52.7% logic, 47.3% route) 

結構、タイミング・エラーが発生しているので、Vivado HLS 2014.1 に戻って、タイミング制約を変更してみようと思う。