create_clock -period 4.000 -name ap_clk -waveform {0.000 2.000} [get_ports ap_clk]
`default_nettype none
module laplcian_filter_top #(
parameter integer INPUT_FF_NUMBER = 1,
parameter integer OUTPUT_FF_NUMBER = 1
)(
input wire ap_clk,
input wire ap_rst,
input wire ap_start,
output wire ap_done,
output wire ap_idle,
output wire ap_ready,
input wire [31:0] xy,
output wire [31:0] ap_return
);
wire [31:0] x0y0;
wire [31:0] x1y0;
wire [31:0] x2y0;
wire [31:0] x0y1;
wire [31:0] x1y1;
wire [31:0] x2y1;
wire [31:0] x0y2;
wire [31:0] x1y2;
wire [31:0] x2y2;
reg [31:0] xy_d[8:0];
wire ap_done_node;
wire ap_idle_node;
wire ap_ready_node;
wire [31:0] ap_return_node;
reg [31:0] x0y0_d [INPUT_FF_NUMBER-1:0];
reg [31:0] x1y0_d [INPUT_FF_NUMBER-1:0];
reg [31:0] x2y0_d [INPUT_FF_NUMBER-1:0];
reg [31:0] x0y1_d [INPUT_FF_NUMBER-1:0];
reg [31:0] x1y1_d [INPUT_FF_NUMBER-1:0];
reg [31:0] x2y1_d [INPUT_FF_NUMBER-1:0];
reg [31:0] x0y2_d [INPUT_FF_NUMBER-1:0];
reg [31:0] x1y2_d [INPUT_FF_NUMBER-1:0];
reg [31:0] x2y2_d [INPUT_FF_NUMBER-1:0];
reg [31:0] ap_return_d [OUTPUT_FF_NUMBER-1:0];
reg [INPUT_FF_NUMBER-1:0] ap_start_d;
reg [OUTPUT_FF_NUMBER-1:0] ap_done_d;
reg [OUTPUT_FF_NUMBER-1:0] ap_idle_d;
reg [OUTPUT_FF_NUMBER-1:0] ap_ready_d;
laplacian_filter lap_filter_inst (
.ap_clk(ap_clk),
.ap_rst(ap_rst),
.ap_start(ap_start_d[0]),
.ap_done(ap_done_node),
.ap_idle(ap_idle_node),
.ap_ready(ap_ready_node),
.x0y0(x0y0_d[0]),
.x1y0(x1y0_d[0]),
.x2y0(x2y0_d[0]),
.x0y1(x0y1_d[0]),
.x1y1(x1y1_d[0]),
.x2y1(x2y1_d[0]),
.x0y2(x0y2_d[0]),
.x1y2(x1y2_d[0]),
.x2y2(x2y2_d[0]),
.ap_return(ap_return_node)
);
always @(posedge ap_clk) begin : AP_XY_DELAY
integer i;
for(i=8; i>=0; i=i-1) begin
if (ap_rst) begin
xy_d[i] <= 32'd0;
end else begin
if (i == 8) begin
xy_d[i] <= xy;
end else begin
xy_d[i] <= xy_d[i+1];
end
end
end
end
assign x0y0 = xy_d[0];
assign x1y0 = xy_d[1];
assign x2y0 = xy_d[2];
assign x0y1 = xy_d[3];
assign x1y1 = xy_d[4];
assign x2y1 = xy_d[5];
assign x0y2 = xy_d[6];
assign x1y2 = xy_d[7];
assign x2y2 = xy_d[8];
always @(posedge ap_clk) begin : AP_START_DELAY
integer i;
for(i=INPUT_FF_NUMBER-1; i>=0; i=i-1) begin
if (ap_rst) begin
ap_start_d[i] <= 1'b0;
end else begin
if (i == (INPUT_FF_NUMBER-1)) begin
ap_start_d[i] <= ap_start;
end else begin
ap_start_d[i] <= ap_start_d[i+1];
end
end
end
end
always @(posedge ap_clk) begin : AP_DONE_DELAY
integer i;
for(i=OUTPUT_FF_NUMBER-1; i>=0; i=i-1) begin
if (ap_rst) begin
ap_done_d[i] <= 1'b0;
end else begin
if (i == (OUTPUT_FF_NUMBER-1)) begin
ap_done_d[i] <= ap_done_node;
end else begin
ap_done_d[i] <= ap_done_d[i+1];
end
end
end
end
assign ap_done = ap_done_d[0];
always @(posedge ap_clk) begin : AP_IDLE_DELAY
integer i;
for(i=OUTPUT_FF_NUMBER-1; i>=0; i=i-1) begin
if (ap_rst) begin
ap_idle_d[i] <= 1'b0;
end else begin
if (i == (OUTPUT_FF_NUMBER-1)) begin
ap_idle_d[i] <= ap_idle_node;
end else begin
ap_idle_d[i] <= ap_idle_d[i+1];
end
end
end
end
assign ap_idle = ap_idle_d[0];
always @(posedge ap_clk) begin : AP_READY_DELAY
integer i;
for(i=OUTPUT_FF_NUMBER-1; i>=0; i=i-1) begin
if (ap_rst) begin
ap_ready_d[i] <= 1'b0;
end else begin
if (i == (OUTPUT_FF_NUMBER-1)) begin
ap_ready_d[i] <= ap_ready_node;
end else begin
ap_ready_d[i] <= ap_ready_d[i+1];
end
end
end
end
assign ap_ready = ap_ready_d[0];
always @(posedge ap_clk) begin : AP_X0Y0_DELAY
integer i;
for(i=INPUT_FF_NUMBER-1; i>=0; i=i-1) begin
if (ap_rst) begin
x0y0_d[i] <= 32'd0;
end else begin
if (i == (INPUT_FF_NUMBER-1)) begin
x0y0_d[i] <= x0y0;
end else begin
x0y0_d[i] <= x0y0_d[i+1];
end
end
end
end
always @(posedge ap_clk) begin : AP_X1Y0_DELAY
integer i;
for(i=INPUT_FF_NUMBER-1; i>=0; i=i-1) begin
if (ap_rst) begin
x1y0_d[i] <= 32'd0;
end else begin
if (i == (INPUT_FF_NUMBER-1)) begin
x1y0_d[i] <= x1y0;
end else begin
x1y0_d[i] <= x1y0_d[i+1];
end
end
end
end
always @(posedge ap_clk) begin : AP_X2Y0_DELAY
integer i;
for(i=INPUT_FF_NUMBER-1; i>=0; i=i-1) begin
if (ap_rst) begin
x2y0_d[i] <= 32'd0;
end else begin
if (i == (INPUT_FF_NUMBER-1)) begin
x2y0_d[i] <= x2y0;
end else begin
x2y0_d[i] <= x2y0_d[i+1];
end
end
end
end
always @(posedge ap_clk) begin : AP_X0Y1_DELAY
integer i;
for(i=INPUT_FF_NUMBER-1; i>=0; i=i-1) begin
if (ap_rst) begin
x0y1_d[i] <= 32'd0;
end else begin
if (i == (INPUT_FF_NUMBER-1)) begin
x0y1_d[i] <= x0y1;
end else begin
x0y1_d[i] <= x0y1_d[i+1];
end
end
end
end
always @(posedge ap_clk) begin : AP_X1Y1_DELAY
integer i;
for(i=INPUT_FF_NUMBER-1; i>=0; i=i-1) begin
if (ap_rst) begin
x1y1_d[i] <= 32'd0;
end else begin
if (i == (INPUT_FF_NUMBER-1)) begin
x1y1_d[i] <= x1y1;
end else begin
x1y1_d[i] <= x1y1_d[i+1];
end
end
end
end
always @(posedge ap_clk) begin : AP_X2Y1_DELAY
integer i;
for(i=INPUT_FF_NUMBER-1; i>=0; i=i-1) begin
if (ap_rst) begin
x2y1_d[i] <= 32'd0;
end else begin
if (i == (INPUT_FF_NUMBER-1)) begin
x2y1_d[i] <= x2y1;
end else begin
x2y1_d[i] <= x2y1_d[i+1];
end
end
end
end
always @(posedge ap_clk) begin : AP_X0Y2_DELAY
integer i;
for(i=INPUT_FF_NUMBER-1; i>=0; i=i-1) begin
if (ap_rst) begin
x0y2_d[i] <= 32'd0;
end else begin
if (i == (INPUT_FF_NUMBER-1)) begin
x0y2_d[i] <= x0y2;
end else begin
x0y2_d[i] <= x0y2_d[i+1];
end
end
end
end
always @(posedge ap_clk) begin : AP_X1Y2_DELAY
integer i;
for(i=INPUT_FF_NUMBER-1; i>=0; i=i-1) begin
if (ap_rst) begin
x1y2_d[i] <= 32'd0;
end else begin
if (i == (INPUT_FF_NUMBER-1)) begin
x1y2_d[i] <= x1y2;
end else begin
x1y2_d[i] <= x1y2_d[i+1];
end
end
end
end
always @(posedge ap_clk) begin : AP_X2Y2_DELAY
integer i;
for(i=INPUT_FF_NUMBER-1; i>=0; i=i-1) begin
if (ap_rst) begin
x2y2_d[i] <= 32'd0;
end else begin
if (i == (INPUT_FF_NUMBER-1)) begin
x2y2_d[i] <= x2y2;
end else begin
x2y2_d[i] <= x2y2_d[i+1];
end
end
end
end
always @(posedge ap_clk) begin : AP_RETURN_DELAY
integer i;
for(i=OUTPUT_FF_NUMBER-1; i>=0; i=i-1) begin
if (ap_rst) begin
ap_return_d[i] <= 32'd0;
end else begin
if (i == (OUTPUT_FF_NUMBER-1)) begin
ap_return_d[i] <= ap_return_node;
end else begin
ap_return_d[i] <= ap_return_d[i+1];
end
end
end
end
assign ap_return = ap_return_d[0];
endmodule
`default_nettype wire
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