SDSoC 2016.2 でラプラシアンフィルタをテスト3

”SDSoC 2016.2 でラプラシアンフィルタをテスト2”の続き。

前回、SDSoC 2015.2 と同様に SDSoC 2016.2 でも 800 x 600 ピクセルの画像をラプラシアンフィルタ処理することはできなかった。それで、前回同様に、64 x 48 ピクセルでやってみることにした。

64 x 48 ピクセルの画像を指定した。例によって使用している 'A' の画像にした。


お気づきと思うが、すでにラプラシアンフィルタ処理の実装をビルドしてある。やはり小さいサイズであればビルドできた。

lap_filter2\SDRelease\sd_card フォルダの内容と temp.bmp（'A'の画像）を MicroSD カードに書き込んだ。


Micro SD カードをZYBO に挿入してテストしてみた。

ZYBO 上でLinux が起動した。
mnt ディレクトリに移動して ./lap_filter2.elf を実行して、実行時間を見た。


最初の実行では、ハードウェアが 641 us に対して、ソフトウェアが 362 us となって 2 倍近くハードウェアの方が遅かった。しかしその後、ハードウェアのラプラシアンフィルタ処理時間はかなりばらついた。ソフトウェアの実行時間もハードウェアよりはばらつきが少ないがやはりばらついている。

ZYBO の電源をOFF して MicroSD カードを見ると、temp_lap.bmp が増えていた。


temp_lap.bmp を開いてみると、きちんとエッジの画像になっていた。


レポートを見てみよう。
lap_filter2\SDRelease\_sds\reports\data_motion.html を見てみよう。


cam_fb と lap_fb に AXIDMA_SG が使用されている。スキャッター・ギャザーDMA だ。

lap_filter2\SDRelease\_sds\reports\sds.rpt を貼っておく。

(c) Copyright 2012-2016 Xilinx, Inc. All Rights Reserved.
#-----------------------------------------------------------
# Tool version : sds++ 2016.2 SW Build on Jul 15 2016 19:20:29
# Start time : Fri Dec 02 04:17:56 +0900 2016
# Command line : sds++ -o lap_filter2.elf ./src/lap_filter_tb.o ./src/laplacian_filter2.o -dmclkid 1 -sds-pf zybo
# Log file : C:/Users/Masaaki/workspace/lap_filter2/SDRelease/_sds/reports/sds.log
# Journal file : C:/Users/Masaaki/workspace/lap_filter2/SDRelease/_sds/reports/sds.jou
# Report file : C:/Users/Masaaki/workspace/lap_filter2/SDRelease/_sds/reports/sds.rpt
#-----------------------------------------------------------

-------------------
Design Timing Check
-------------------

Partition 0
Vivado Log : C:/Users/Masaaki/workspace/lap_filter2/SDRelease/_sds/p0/ipi/vivado.log
Timing Summary : C:/Users/Masaaki/workspace/lap_filter2/SDRelease/_sds/p0/ipi/zybo.runs/impl_1/zybo_wrapper_timing_summary_routed.rpt

All user specified timing constraints are met.

Timing Summary Report

Timer Settings
--------------

Enable Multi Corner Analysis : Yes
Enable Pessimism Removal : Yes
Pessimism Removal Resolution : Nearest Common Node
Enable Input Delay Default Clock : No
Enable Preset / Clear Arcs : No
Disable Flight Delays : No
Ignore I/O Paths : No
Timing Early Launch at Borrowing Latches : false

Corner Analyze Analyze
Name Max Paths Min Paths
------ --------- ---------
Slow Yes Yes
Fast Yes Yes



check_timing report

Table of Contents
1. checking no_clock
2. checking constant_clock
3. checking pulse_width_clock
4. checking unconstrained_internal_endpoints
5. checking no_input_delay
6. checking no_output_delay
7. checking multiple_clock
8. checking generated_clocks
9. checking loops
10. checking partial_input_delay
11. checking partial_output_delay
12. checking latch_loops

1. checking no_clock
There are 0 register/latch pins with no clock.


2. checking constant_clock
There are 0 register/latch pins with constant_clock.


3. checking pulse_width_clock
There are 0 register/latch pins which need pulse_width check


4. checking unconstrained_internal_endpoints
There are 0 pins that are not constrained for maximum delay.

There are 0 pins that are not constrained for maximum delay due to constant clock.


5. checking no_input_delay
There are 0 input ports with no input delay specified.

There are 0 input ports with no input delay but user has a false path constraint.


6. checking no_output_delay
There are 0 ports with no output delay specified.

There are 0 ports with no output delay but user has a false path constraint

There are 0 ports with no output delay but with a timing clock defined on it or propagating through it


7. checking multiple_clock
There are 0 register/latch pins with multiple clocks.


8. checking generated_clocks
There are 0 generated clocks that are not connected to a clock source.


9. checking loops
There are 0 combinational loops in the design.


10. checking partial_input_delay
There are 0 input ports with partial input delay specified.


11. checking partial_output_delay
There are 0 ports with partial output delay specified.


12. checking latch_loops
There are 0 combinational latch loops in the design through latch input



Design Timing Summary
---------------------

WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
2.599 0.000 0 34698 0.036 0.000 0 34698 3.870 0.000 0 12722


All user specified timing constraints are met.


Clock Summary
-------------

Clock Waveform(ns) Period(ns) Frequency(MHz)
----- ------------ ---------- --------------
clk_fpga_0 {0.000 20.000} 40.000 25.000
clk_fpga_1 {0.000 5.000} 10.000 100.000
clk_fpga_2 {0.000 4.000} 8.000 125.000
clk_fpga_3 {0.000 10.000} 20.000 50.000


-------------------
Data Motion Network
-------------------

Data motion network report generated in C:/Users/Masaaki/workspace/lap_filter2/SDRelease/_sds/reports
HTML file : C:/Users/Masaaki/workspace/lap_filter2/SDRelease/_sds/reports/data_motion.html

-------------------
Design Utilization
-------------------

Partition 0
Utilization Summary : C:/Users/Masaaki/workspace/lap_filter2/SDRelease/_sds/p0/ipi/zybo.runs/impl_1/zybo_wrapper_utilization_placed.rpt

Utilization Design Information

Table of Contents
-----------------
1. Slice Logic
1.1 Summary of Registers by Type
2. Slice Logic Distribution
3. Memory
4. DSP
5. IO and GT Specific
6. Clocking
7. Specific Feature
8. Primitives
9. Black Boxes
10. Instantiated Netlists

1. Slice Logic
--------------

+----------------------------+-------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+----------------------------+-------+-------+-----------+-------+
| Slice LUTs | 7513 | 0 | 17600 | 42.69 |
| LUT as Logic | 6799 | 0 | 17600 | 38.63 |
| LUT as Memory | 714 | 0 | 6000 | 11.90 |
| LUT as Distributed RAM | 456 | 0 | | |
| LUT as Shift Register | 258 | 0 | | |
| Slice Registers | 11408 | 0 | 35200 | 32.41 |
| Register as Flip Flop | 11408 | 0 | 35200 | 32.41 |
| Register as Latch | 0 | 0 | 35200 | 0.00 |
| F7 Muxes | 74 | 0 | 8800 | 0.84 |
| F8 Muxes | 1 | 0 | 4400 | 0.02 |
+----------------------------+-------+-------+-----------+-------+


1.1 Summary of Registers by Type
--------------------------------

+-------+--------------+-------------+--------------+
| Total | Clock Enable | Synchronous | Asynchronous |
+-------+--------------+-------------+--------------+
| 0 | _ | - | - |
| 0 | _ | - | Set |
| 0 | _ | - | Reset |
| 0 | _ | Set | - |
| 0 | _ | Reset | - |
| 0 | Yes | - | - |
| 342 | Yes | - | Set |
| 628 | Yes | - | Reset |
| 222 | Yes | Set | - |
| 10216 | Yes | Reset | - |
+-------+--------------+-------------+--------------+


2. Slice Logic Distribution
---------------------------

+------------------------------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+------------------------------------------+------+-------+-----------+-------+
| Slice | 3398 | 0 | 4400 | 77.23 |
| SLICEL | 2235 | 0 | | |
| SLICEM | 1163 | 0 | | |
| LUT as Logic | 6799 | 0 | 17600 | 38.63 |
| using O5 output only | 1 | | | |
| using O6 output only | 5271 | | | |
| using O5 and O6 | 1527 | | | |
| LUT as Memory | 714 | 0 | 6000 | 11.90 |
| LUT as Distributed RAM | 456 | 0 | | |
| using O5 output only | 0 | | | |
| using O6 output only | 52 | | | |
| using O5 and O6 | 404 | | | |
| LUT as Shift Register | 258 | 0 | | |
| using O5 output only | 0 | | | |
| using O6 output only | 117 | | | |
| using O5 and O6 | 141 | | | |
| LUT Flip Flop Pairs | 3966 | 0 | 17600 | 22.53 |
| fully used LUT-FF pairs | 953 | | | |
| LUT-FF pairs with one unused LUT | 2819 | | | |
| LUT-FF pairs with one unused Flip Flop | 2684 | | | |
| Unique Control Sets | 599 | | | |
+------------------------------------------+------+-------+-----------+-------+
* Note: Review the Control Sets Report for more information regarding control sets.


3. Memory
---------

+-------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------------+------+-------+-----------+-------+
| Block RAM Tile | 21 | 0 | 60 | 35.00 |
| RAMB36/FIFO* | 18 | 0 | 60 | 30.00 |
| RAMB36E1 only | 18 | | | |
| RAMB18 | 6 | 0 | 120 | 5.00 |
| RAMB18E1 only | 6 | | | |
+-------------------+------+-------+-----------+-------+
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1


4. DSP
------

+----------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+----------------+------+-------+-----------+-------+
| DSPs | 10 | 0 | 80 | 12.50 |
| DSP48E1 only | 10 | | | |
+----------------+------+-------+-----------+-------+


5. IO and GT Specific
---------------------

+-----------------------------+------+-------+-----------+--------+
| Site Type | Used | Fixed | Available | Util% |
+-----------------------------+------+-------+-----------+--------+
| Bonded IOB | 0 | 0 | 100 | 0.00 |
| Bonded IPADs | 0 | 0 | 2 | 0.00 |
| Bonded IOPADs | 130 | 130 | 130 | 100.00 |
| PHY_CONTROL | 0 | 0 | 2 | 0.00 |
| PHASER_REF | 0 | 0 | 2 | 0.00 |
| OUT_FIFO | 0 | 0 | 8 | 0.00 |
| IN_FIFO | 0 | 0 | 8 | 0.00 |
| IDELAYCTRL | 0 | 0 | 2 | 0.00 |
| IBUFDS | 0 | 0 | 96 | 0.00 |
| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 8 | 0.00 |
| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 8 | 0.00 |
| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 100 | 0.00 |
| ILOGIC | 0 | 0 | 100 | 0.00 |
| OLOGIC | 0 | 0 | 100 | 0.00 |
+-----------------------------+------+-------+-----------+--------+


6. Clocking
-----------

+------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+------------+------+-------+-----------+-------+
| BUFGCTRL | 1 | 0 | 32 | 3.13 |
| BUFIO | 0 | 0 | 8 | 0.00 |
| MMCME2_ADV | 0 | 0 | 2 | 0.00 |
| PLLE2_ADV | 0 | 0 | 2 | 0.00 |
| BUFMRCE | 0 | 0 | 4 | 0.00 |
| BUFHCE | 0 | 0 | 48 | 0.00 |
| BUFR | 0 | 0 | 8 | 0.00 |
+------------+------+-------+-----------+-------+


7. Specific Feature
-------------------

+-------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------+------+-------+-----------+-------+
| BSCANE2 | 0 | 0 | 4 | 0.00 |
| CAPTUREE2 | 0 | 0 | 1 | 0.00 |
| DNA_PORT | 0 | 0 | 1 | 0.00 |
| EFUSE_USR | 0 | 0 | 1 | 0.00 |
| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 |
| ICAPE2 | 0 | 0 | 2 | 0.00 |
| STARTUPE2 | 0 | 0 | 1 | 0.00 |
| XADC | 0 | 0 | 1 | 0.00 |
+-------------+------+-------+-----------+-------+


8. Primitives
-------------

+----------+-------+----------------------+
| Ref Name | Used | Functional Category |
+----------+-------+----------------------+
| FDRE | 10216 | Flop & Latch |
| LUT3 | 2303 | LUT |
| LUT6 | 1835 | LUT |
| LUT4 | 1434 | LUT |
| LUT5 | 1219 | LUT |
| LUT2 | 1171 | LUT |
| FDCE | 628 | Flop & Latch |
| RAMD32 | 610 | Distributed Memory |
| LUT1 | 364 | LUT |
| FDPE | 342 | Flop & Latch |
| CARRY4 | 339 | CarryLogic |
| SRL16E | 338 | Distributed Memory |
| FDSE | 222 | Flop & Latch |
| RAMS32 | 202 | Distributed Memory |
| BIBUF | 130 | IO |
| MUXF7 | 74 | MuxFx |
| SRLC32E | 61 | Distributed Memory |
| RAMD64E | 48 | Distributed Memory |
| RAMB36E1 | 18 | Block Memory |
| DSP48E1 | 10 | Block Arithmetic |
| RAMB18E1 | 6 | Block Memory |
| PS7 | 1 | Specialized Resource |
| MUXF8 | 1 | MuxFx |
| BUFG | 1 | Clock |
+----------+-------+----------------------+


9. Black Boxes
--------------

+----------+------+
| Ref Name | Used |
+----------+------+


10. Instantiated Netlists
-------------------------

+-----------------------------+------+
| Ref Name | Used |
+-----------------------------+------+
| zybo_xlconcat_0 | 1 |
| zybo_xbar_1 | 1 |
| zybo_xbar_0 | 1 |
| zybo_s02_regslice_0 | 1 |
| zybo_s02_data_fifo_0 | 1 |
| zybo_s01_regslice_0 | 1 |
| zybo_s01_data_fifo_0 | 1 |
| zybo_s00_regslice_1 | 1 |
| zybo_s00_regslice_0 | 1 |
| zybo_s00_data_fifo_0 | 1 |
| zybo_ps7_0 | 1 |
| zybo_proc_sys_reset_1_0 | 1 |
| zybo_m01_regslice_0 | 1 |
| zybo_m00_regslice_1 | 1 |
| zybo_m00_regslice_0 | 1 |
| zybo_m00_data_fifo_0 | 1 |
| zybo_lap_filter_axim_0_if_0 | 1 |
| zybo_lap_filter_axim_0_0 | 1 |
| zybo_dm_0_0 | 1 |
| zybo_axis_rtr_dm_0_0 | 1 |
| zybo_auto_us_df_0 | 1 |
| zybo_auto_pc_1 | 1 |
| zybo_auto_pc_0 | 1 |
| zybo_acp_axcache_0xE_0 | 1 |
| zybo_acp_axcache_0x2_0 | 1 |
+-----------------------------+------+