// usonic_sensor_inf.v
// 2016/12/12 by marsee
//
`default_nettype none
module usonic_sensor_inf #(
parameter ap_const_int64_8 = 8,
parameter C_S_AXI_AXILITES_DATA_WIDTH = 32,
parameter C_S_AXI_AXILITES_ADDR_WIDTH = 5,
parameter C_S_AXI_DATA_WIDTH = 32,
parameter C_S_AXI_AXILITES_WSTRB_WIDTH = (C_S_AXI_AXILITES_DATA_WIDTH / ap_const_int64_8),
parameter C_S_AXI_WSTRB_WIDTH = (C_S_AXI_DATA_WIDTH / ap_const_int64_8)
)(
input wire ap_clk, // Clock
input wire ap_rst_n, // Asynchronous reset active low
inout wire ussensor_inout,
input wire s_axi_AXILiteS_AWVALID,
output wire s_axi_AXILiteS_AWREADY,
input wire [C_S_AXI_AXILITES_ADDR_WIDTH - 1 : 0] s_axi_AXILiteS_AWADDR,
input wire s_axi_AXILiteS_WVALID,
output wire s_axi_AXILiteS_WREADY,
input wire [C_S_AXI_AXILITES_DATA_WIDTH - 1 : 0] s_axi_AXILiteS_WDATA,
input wire [C_S_AXI_AXILITES_WSTRB_WIDTH - 1 : 0] s_axi_AXILiteS_WSTRB,
input wire s_axi_AXILiteS_ARVALID,
output wire s_axi_AXILiteS_ARREADY,
input wire [C_S_AXI_AXILITES_ADDR_WIDTH - 1 : 0] s_axi_AXILiteS_ARADDR,
output wire s_axi_AXILiteS_RVALID,
input wire s_axi_AXILiteS_RREADY,
output wire [C_S_AXI_AXILITES_DATA_WIDTH - 1 : 0] s_axi_AXILiteS_RDATA,
output wire [1:0] s_axi_AXILiteS_RRESP,
output wire s_axi_AXILiteS_BVALID,
input wire s_axi_AXILiteS_BREADY,
output wire [1:0] s_axi_AXILiteS_BRESP,
output wire interrupt
);
wire sensor_out_V;
wire sensor_out_en_V;
wire sensor_in_V_V;
wire sensor_in_V_V_ap_vld;
wire sensor_in_V_V_ap_ack;
IOBUF ussensor_iobuf(
.I(sensor_out_V),
.IO(ussensor_inout),
.O(sensor_in_V_V),
.T(!sensor_out_en_V)
);
assign sensor_in_V_V_ap_vld = 1'b1;
ultrasonic_sensor_inf ussensor_inf_i (
.ap_clk (ap_clk),
.ap_rst_n (ap_rst_n),
.sensor_out_V (sensor_out_V),
.sensor_out_en_V (sensor_out_en_V),
.sensor_in_V_V (sensor_in_V_V),
.sensor_in_V_V_ap_vld (sensor_in_V_V_ap_vld),
.sensor_in_V_V_ap_ack (sensor_in_V_V_ap_ack),
.s_axi_AXILiteS_AWVALID (s_axi_AXILiteS_AWVALID),
.s_axi_AXILiteS_AWREADY (s_axi_AXILiteS_AWREADY),
.s_axi_AXILiteS_AWADDR (s_axi_AXILiteS_AWADDR),
.s_axi_AXILiteS_WVALID (s_axi_AXILiteS_WVALID),
.s_axi_AXILiteS_WREADY (s_axi_AXILiteS_WREADY),
.s_axi_AXILiteS_WDATA (s_axi_AXILiteS_WDATA),
.s_axi_AXILiteS_WSTRB (s_axi_AXILiteS_WSTRB),
.s_axi_AXILiteS_ARVALID (s_axi_AXILiteS_ARVALID),
.s_axi_AXILiteS_ARREADY (s_axi_AXILiteS_ARREADY),
.s_axi_AXILiteS_ARADDR (s_axi_AXILiteS_ARADDR),
.s_axi_AXILiteS_RVALID (s_axi_AXILiteS_RVALID),
.s_axi_AXILiteS_RREADY (s_axi_AXILiteS_RREADY),
.s_axi_AXILiteS_RDATA (s_axi_AXILiteS_RDATA),
.s_axi_AXILiteS_RRESP (s_axi_AXILiteS_RRESP),
.s_axi_AXILiteS_BVALID (s_axi_AXILiteS_BVALID),
.s_axi_AXILiteS_BREADY (s_axi_AXILiteS_BREADY),
.s_axi_AXILiteS_BRESP (s_axi_AXILiteS_BRESP),
.interrupt (interrupt)
);
endmodule
`default_nettype wire
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