set_property IOSTANDARD LVCMOS33 [get_ports {cam_data[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {cam_data[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {cam_data[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {cam_data[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {cam_data[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {cam_data[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {cam_data[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {cam_data[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports mt9d111_iic_scl_io]
set_property IOSTANDARD LVCMOS33 [get_ports mt9d111_iic_sda_io]
set_property IOSTANDARD LVCMOS33 [get_ports href]
set_property IOSTANDARD LVCMOS33 [get_ports pclk]
set_property IOSTANDARD LVCMOS33 [get_ports standby]
set_property IOSTANDARD LVCMOS33 [get_ports vsync]
set_property IOSTANDARD LVCMOS33 [get_ports xck]
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets pclk_IBUF]
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets pclk_IBUF_BUFG]
create_clock -period 55.560 -name pclk -waveform {0.000 27.780} [get_ports pclk]
set_input_delay -clock [get_clocks pclk] 10.800 [get_ports {{cam_data[0]} {cam_data[1]} {cam_data[2]} {cam_data[3]} {cam_data[4]} {cam_data[5]} {cam_data[6]} {cam_data[7]} href pclk vsync}]
set_property PULLUP true [get_ports mt9d111_iic_scl_io]
set_property PULLUP true [get_ports mt9d111_iic_sda_io]
set_property PACKAGE_PIN W14 [get_ports {cam_data[7]}]
set_property PACKAGE_PIN V16 [get_ports {cam_data[6]}]
set_property PACKAGE_PIN Y14 [get_ports {cam_data[5]}]
set_property PACKAGE_PIN W16 [get_ports {cam_data[4]}]
set_property PACKAGE_PIN T11 [get_ports {cam_data[3]}]
set_property PACKAGE_PIN V12 [get_ports {cam_data[2]}]
set_property PACKAGE_PIN T10 [get_ports {cam_data[1]}]
set_property PACKAGE_PIN W13 [get_ports {cam_data[0]}]
set_property IOSTANDARD TMDS_33 [get_ports TMDS_tx_0_B_p]
set_property IOSTANDARD TMDS_33 [get_ports TMDS_tx_1_R_p]
set_property IOSTANDARD TMDS_33 [get_ports TMDS_tx_2_G_p]
set_property IOSTANDARD TMDS_33 [get_ports TMDS_tx_clk_p]
set_property PACKAGE_PIN U19 [get_ports href]
set_property PACKAGE_PIN Y16 [get_ports standby]
set_property PACKAGE_PIN K17 [get_ports TMDS_tx_0_B_p]
set_property PACKAGE_PIN K19 [get_ports TMDS_tx_1_R_p]
set_property PACKAGE_PIN J18 [get_ports TMDS_tx_2_G_p]
set_property PACKAGE_PIN L16 [get_ports TMDS_tx_clk_p]
set_property PACKAGE_PIN Y19 [get_ports vsync]
set_property PACKAGE_PIN W19 [get_ports xck]
set_property PACKAGE_PIN Y18 [get_ports mt9d111_iic_scl_io]
set_property PACKAGE_PIN U18 [get_ports mt9d111_iic_sda_io]
set_property PACKAGE_PIN Y17 [get_ports pclk]
set_false_path -from [get_clocks pclk] -to [get_clocks clk_fpga_0]
set_false_path -from [get_clocks clk_fpga_0] -to [get_clocks pclk]
set_false_path -from [get_clocks [get_clocks -of_objects [get_pins pynq_fastx_i/bitmap_disp_cntrler_axi_master_0/inst/dvi_disp_i/BUFR_pixel_clk_io/O]]] -to [get_clocks clk_fpga_0]
日 | 月 | 火 | 水 | 木 | 金 | 土 |
---|---|---|---|---|---|---|
- | - | - | - | - | 1 | 2 |
3 | 4 | 5 | 6 | 7 | 8 | 9 |
10 | 11 | 12 | 13 | 14 | 15 | 16 |
17 | 18 | 19 | 20 | 21 | 22 | 23 |
24 | 25 | 26 | 27 | 28 | 29 | 30 |
31 | - | - | - | - | - | - |