component void vector_add(int* a,
int* b,
int* c,
int N) {
for (int i = 0; i < N; ++i) {
c[i] = a[i] + b[i];
}
}
component void vector_add(ihc::mm_master<int, ihc::aspace<1>, ihc::awidth<16>, ihc::dwidth<32> >& a,
ihc::mm_master<int, ihc::aspace<2>, ihc::awidth<16>, ihc::dwidth<32> >& b,
ihc::mm_master<int, ihc::aspace<3>, ihc::awidth<16>, ihc::dwidth<32> >& c,
int N) {
for (int i = 0; i < N; ++i) {
c[i] = a[i] + b[i];
}
}
component void vector_add(ihc::mm_master<int, ihc::aspace<1>, ihc::awidth<32>, ihc::dwidth<256>, ihc::latency<0>, ihc::maxburst<8>, ihc::waitrequest<true> >& a, // bank 1
ihc::mm_master<int, ihc::aspace<1>, ihc::awidth<32>, ihc::dwidth<256>, ihc::latency<0>, ihc::maxburst<8>, ihc::waitrequest<true> >& b, // bank 1
ihc::mm_master<int, ihc::aspace<2>, ihc::awidth<32>, ihc::dwidth<256>, ihc::latency<0>, ihc::maxburst<8>, ihc::waitrequest<true> >& c, // bank 2
int N) {
for (int i = 0; i < N; ++i) {
c[i] = a[i] + b[i];
}
}
component void vector_add(ihc::mm_master<int, ihc::aspace<1>, ihc::awidth<32>, ihc::dwidth<256>, ihc::latency<0>, ihc::maxburst<8>, ihc::waitrequest<true> >& a, // bank 1
ihc::mm_master<int, ihc::aspace<1>, ihc::awidth<32>, ihc::dwidth<256>, ihc::latency<0>, ihc::maxburst<8>, ihc::waitrequest<true> >& b, // bank 1
ihc::mm_master<int, ihc::aspace<2>, ihc::awidth<32>, ihc::dwidth<256>, ihc::latency<0>, ihc::maxburst<8>, ihc::waitrequest<true> >& c, // bank 2
int N) {
#pragma unroll 8
for (int i = 0; i < N; ++i) {
c[i] = a[i] + b[i];
}
}
component void vector_add(ihc::mm_master<int, ihc::aspace<1>, ihc::awidth<32>, ihc::dwidth<256>, ihc::latency<0>, ihc::maxburst<8>, ihc::align<32>, ihc::waitrequest<true> >& a, // bank 1
ihc::mm_master<int, ihc::aspace<1>, ihc::awidth<32>, ihc::dwidth<256>, ihc::latency<0>, ihc::maxburst<8>, ihc::align<32>, ihc::waitrequest<true> >& b, // bank 1
ihc::mm_master<int, ihc::aspace<2>, ihc::awidth<32>, ihc::dwidth<256>, ihc::latency<0>, ihc::maxburst<8>, ihc::align<32>, ihc::waitrequest<true> >& c, // bank 2
int N) {
#pragma unroll 8
for (int i = 0; i < N; ++i) {
c[i] = a[i] + b[i];
}
}
vector_add vector_add_inst (
// Interface: clock (clock end)
.clock ( ), // 1-bit clk input
// Interface: reset (reset end)
.resetn ( ), // 1-bit reset_n input
// Interface: call (conduit sink)
.start ( ), // 1-bit valid input
.busy ( ), // 1-bit stall output
// Interface: return (conduit source)
.done ( ), // 1-bit valid output
.stall ( ), // 1-bit stall input
// Interface: a (conduit sink)
.a ( ), // 64-bit data input
// Interface: b (conduit sink)
.b ( ), // 64-bit data input
// Interface: c (conduit sink)
.c ( ), // 64-bit data input
// Interface: N (conduit sink)
.N ( ), // 32-bit data input
// Interface: avmm_0_rw (avalon start)
.avmm_0_rw_address ( ), // 64-bit address output
.avmm_0_rw_byteenable( ), // 8-bit byteenable output
.avmm_0_rw_read ( ), // 1-bit read output
.avmm_0_rw_readdata ( ), // 64-bit readdata input
.avmm_0_rw_write ( ), // 1-bit write output
.avmm_0_rw_writedata ( ) // 64-bit writedata output
);
vector_add vector_add_inst (
// Interface: clock (clock end)
.clock ( ), // 1-bit clk input
// Interface: reset (reset end)
.resetn ( ), // 1-bit reset_n input
// Interface: call (conduit sink)
.start ( ), // 1-bit valid input
.busy ( ), // 1-bit stall output
// Interface: return (conduit source)
.done ( ), // 1-bit valid output
.stall ( ), // 1-bit stall input
// Interface: a (conduit sink)
.a ( ), // 64-bit data input
// Interface: b (conduit sink)
.b ( ), // 64-bit data input
// Interface: c (conduit sink)
.c ( ), // 64-bit data input
// Interface: N (conduit sink)
.N ( ), // 32-bit data input
// Interface: avmm_1_rw (avalon start)
.avmm_1_rw_address ( ), // 16-bit address output
.avmm_1_rw_byteenable( ), // 4-bit byteenable output
.avmm_1_rw_read ( ), // 1-bit read output
.avmm_1_rw_readdata ( ), // 32-bit readdata input
.avmm_1_rw_write ( ), // 1-bit write output
.avmm_1_rw_writedata ( ), // 32-bit writedata output
// Interface: avmm_2_rw (avalon start)
.avmm_2_rw_address ( ), // 16-bit address output
.avmm_2_rw_byteenable( ), // 4-bit byteenable output
.avmm_2_rw_read ( ), // 1-bit read output
.avmm_2_rw_readdata ( ), // 32-bit readdata input
.avmm_2_rw_write ( ), // 1-bit write output
.avmm_2_rw_writedata ( ), // 32-bit writedata output
// Interface: avmm_3_rw (avalon start)
.avmm_3_rw_address ( ), // 16-bit address output
.avmm_3_rw_byteenable( ), // 4-bit byteenable output
.avmm_3_rw_read ( ), // 1-bit read output
.avmm_3_rw_readdata ( ), // 32-bit readdata input
.avmm_3_rw_write ( ), // 1-bit write output
.avmm_3_rw_writedata ( ) // 32-bit writedata output
);
vector_add vector_add_inst (
// Interface: clock (clock end)
.clock ( ), // 1-bit clk input
// Interface: reset (reset end)
.resetn ( ), // 1-bit reset_n input
// Interface: call (conduit sink)
.start ( ), // 1-bit valid input
.busy ( ), // 1-bit stall output
// Interface: return (conduit source)
.done ( ), // 1-bit valid output
.stall ( ), // 1-bit stall input
// Interface: a (conduit sink)
.a ( ), // 64-bit data input
// Interface: b (conduit sink)
.b ( ), // 64-bit data input
// Interface: c (conduit sink)
.c ( ), // 64-bit data input
// Interface: N (conduit sink)
.N ( ), // 32-bit data input
// Interface: avmm_1_rw (avalon start)
.avmm_1_rw_address ( ), // 32-bit address output
.avmm_1_rw_byteenable ( ), // 32-bit byteenable output
.avmm_1_rw_readdatavalid( ), // 1-bit readdatavalid input
.avmm_1_rw_read ( ), // 1-bit read output
.avmm_1_rw_readdata ( ), // 256-bit readdata input
.avmm_1_rw_write ( ), // 1-bit write output
.avmm_1_rw_writedata ( ), // 256-bit writedata output
.avmm_1_rw_waitrequest ( ), // 1-bit waitrequest input
.avmm_1_rw_burstcount ( ), // 4-bit burstcount output
// Interface: avmm_2_rw (avalon start)
.avmm_2_rw_address ( ), // 32-bit address output
.avmm_2_rw_byteenable ( ), // 32-bit byteenable output
.avmm_2_rw_readdatavalid( ), // 1-bit readdatavalid input
.avmm_2_rw_read ( ), // 1-bit read output
.avmm_2_rw_readdata ( ), // 256-bit readdata input
.avmm_2_rw_write ( ), // 1-bit write output
.avmm_2_rw_writedata ( ), // 256-bit writedata output
.avmm_2_rw_waitrequest ( ), // 1-bit waitrequest input
.avmm_2_rw_burstcount ( ) // 4-bit burstcount output
);
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