(base) masaaki@masaaki-H110M4-M01:/media/masaaki/Ubuntu_Disk/KR260/kr260_custom_platform/kr260_custom_platform$ xsct
rlwrap: warning: your $TERM is 'xterm-256color' but rlwrap couldn't find it in the terminfo database. Expect some problems.
****** Xilinx Software Commandline Tool (XSCT) v2022.1.0
**** SW Build 3524075 on 2022-04-13-17:42:45
** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
xsct% createdts -hw /media/masaaki/Ubuntu_Disk/KR260/kr260_custom_platform/kr260_custom_platform/kr260_vadd2_system_hw_link/Hardware/binary_container_1.build/link/vivado/vpl/prj/kr260_custom.xsa -zocl -platform-name kr260_custom -git-branch xlnx_rel_v2022.1 -overlay -compile -out ./dtg/dtg_kr260_ip_vadd
INFO: DTG repo already exists at /media/masaaki/Ubuntu_Disk/KR260/kr260_custom_platform/kr260_custom_platform/dtg/dtg_kr260_ip_vadd/device-tree-xlnx
/media/masaaki/Ubuntu_Disk/KR260/kr260_custom_platform/kr260_custom_platform/dtg/dtg_kr260_ip_vadd/dtg/dtg_kr260_ip_vadd/device-tree-xlnx
INFO: [Hsi 55-2053] elapsed time for repository (/media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2022.1/data/embeddedsw) loading 0 seconds
hsi::open_hw_design: Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 2348.008 ; gain = 0.000 ; free physical = 1481 ; free virtual = 31607
INFO: Creating platform kr260_custom at ./dtg/dtg_kr260_ip_vadd
Opening the hardware design, this may take few seconds.
INFO: Populating the default qemu data for the domain "device_tree_domain" from the install location /media/masaaki/Ubuntu_Disk/tools/Xilinx/Vitis/2022.1/data/emulation/platforms/zynqmp/sw/a53_standalone/qemu/
WARNING: Interrupt pin "interrupt" of IP block: "DMA_pow2_0" is not connected to any interrupt controller
WARNING: Interrupt pin "mm2s_introut" of IP block: "axi_dma_0" is not connected to any interrupt controller
WARNING: Interrupt pin "s2mm_introut" of IP block: "axi_dma_0" is not connected to any interrupt controller
WARNING: Interrupt pin "interrupt" of IP block: "axi_timer_0" is not connected to any interrupt controller
WARNING: no s_axi_aclk for clockwizard IP block: " clk_wiz_0"
WARNING: Clock pin "ap_clk" of IP block "krnl_vadd_1" is not connected to any of the pl_clk"
WARNING: Interrupt pin "interrupt" of IP block: "multi_axi4ls_0" is not connected to any interrupt controller
zocl:false
ext_platform:
WARNING: axi_dma_0 connected ip is NULL for the pin M_AXIS_MM2S
WARNING: axi_dma_0 connected ip is NULL for the pin M_AXIS_MM2S
WARNING: ERROR: axi_dma_0: mm2s_introut port is not connected
WARNING: ERROR: axi_dma_0: s2mm_introut port is not connected
WARNING: label 'usb0' found in existing tree
WARNING: label 'usb1' found in existing tree
INFO: Generating device tree
WARNING: Interrupt pin "interrupt" of IP block: "DMA_pow2_0" is not connected to any interrupt controller
WARNING: Interrupt pin "mm2s_introut" of IP block: "axi_dma_0" is not connected to any interrupt controller
WARNING: Interrupt pin "s2mm_introut" of IP block: "axi_dma_0" is not connected to any interrupt controller
WARNING: Interrupt pin "interrupt" of IP block: "axi_timer_0" is not connected to any interrupt controller
WARNING: no s_axi_aclk for clockwizard IP block: " clk_wiz_0"
WARNING: Clock pin "ap_clk" of IP block "krnl_vadd_1" is not connected to any of the pl_clk"
WARNING: Interrupt pin "interrupt" of IP block: "multi_axi4ls_0" is not connected to any interrupt controller
zocl:true
ext_platform:
intr_ctrl_len:1
WARNING: axi_dma_0 connected ip is NULL for the pin M_AXIS_MM2S
WARNING: axi_dma_0 connected ip is NULL for the pin M_AXIS_MM2S
WARNING: ERROR: axi_dma_0: mm2s_introut port is not connected
WARNING: ERROR: axi_dma_0: s2mm_introut port is not connected
WARNING: label 'usb0' found in existing tree
WARNING: label 'usb1' found in existing tree
Building the BSP Library for domain - device_tree_domain on processor psu_cortexa53_0
make: Nothing to be done for 'all'.
system-top.dts:24.9-27.4: Warning (unit_address_vs_reg): /memory: node has a reg or ranges property, but no unit name
zynqmp.dtsi:811.43-815.6: Warning (pci_device_reg): /axi/pcie@fd0e0000/legacy-interrupt-controller: missing PCI reg property
xsct% exit
(base) masaaki@masaaki-H110M4-M01:/media/masaaki/Ubuntu_Disk/KR260/kr260_custom_platform/kr260_custom_platform$
/*
* CAUTION: This file is automatically generated by Xilinx.
* Version: XSCT 2022.1
* Today is: Sun Mar 19 19:55:06 2023
*/
/dts-v1/;
/plugin/;
/ {
fragment@0 {
target = <&fpga_full>;
overlay0: __overlay__ {
#address-cells = <2>;
#size-cells = <2>;
firmware-name = "kr260_custom.bit.bin";
resets = <&zynqmp_reset 116>, <&zynqmp_reset 117>, <&zynqmp_reset 118>, <&zynqmp_reset 119>;
};
};
fragment@1 {
target = <&amba>;
overlay1: __overlay__ {
afi0: afi0 {
compatible = "xlnx,afi-fpga";
config-afi = < 0 0>, <1 0>, <2 0>, <3 0>, <4 0>, <5 0>, <6 0>, <7 0>, <8 0>, <9 0>, <10 0>, <11 0>, <12 0>, <13 0>, <14 0xa00>, <15 0x000>;
};
clocking0: clocking0 {
#clock-cells = <0>;
assigned-clock-rates = <99999001>;
assigned-clocks = <&zynqmp_clk 71>;
clock-output-names = "fabric_clk";
clocks = <&zynqmp_clk 71>;
compatible = "xlnx,fclk";
};
clocking1: clocking1 {
#clock-cells = <0>;
assigned-clock-rates = <99999001>;
assigned-clocks = <&zynqmp_clk 72>;
clock-output-names = "fabric_clk";
clocks = <&zynqmp_clk 72>;
compatible = "xlnx,fclk";
};
};
};
fragment@2 {
target = <&amba>;
overlay2: __overlay__ {
#address-cells = <2>;
#size-cells = <2>;
DMA_pow2_0: DMA_pow2@80070000 {
/* This is a place holder node for a custom IP, user may need to update the entries */
clock-names = "ap_clk";
clocks = <&zynqmp_clk 71>;
compatible = "generic-uio";
reg = <0x0 0x80070000 0x0 0x10000>;
xlnx,s-axi-control-addr-width = <0x6>;
xlnx,s-axi-control-data-width = <0x20>;
};
PMOD_0: gpio@80010000 {
#gpio-cells = <2>;
clock-names = "s_axi_aclk";
clocks = <&zynqmp_clk 71>;
compatible = "xlnx,axi-gpio-2.0", "xlnx,xps-gpio-1.00.a";
gpio-controller ;
reg = <0x0 0x80010000 0x0 0x10000>;
xlnx,all-inputs = <0x0>;
xlnx,all-inputs-2 = <0x0>;
xlnx,all-outputs = <0x0>;
xlnx,all-outputs-2 = <0x0>;
xlnx,dout-default = <0x00000000>;
xlnx,dout-default-2 = <0x00000000>;
xlnx,gpio-width = <0x8>;
xlnx,gpio2-width = <0x20>;
xlnx,interrupt-present = <0x0>;
xlnx,is-dual = <0x0>;
xlnx,tri-default = <0xFFFFFFFF>;
xlnx,tri-default-2 = <0xFFFFFFFF>;
};
PMOD_1: gpio@80020000 {
#gpio-cells = <2>;
clock-names = "s_axi_aclk";
clocks = <&zynqmp_clk 71>;
compatible = "xlnx,axi-gpio-2.0", "xlnx,xps-gpio-1.00.a";
gpio-controller ;
reg = <0x0 0x80020000 0x0 0x10000>;
xlnx,all-inputs = <0x0>;
xlnx,all-inputs-2 = <0x0>;
xlnx,all-outputs = <0x0>;
xlnx,all-outputs-2 = <0x0>;
xlnx,dout-default = <0x00000000>;
xlnx,dout-default-2 = <0x00000000>;
xlnx,gpio-width = <0x8>;
xlnx,gpio2-width = <0x20>;
xlnx,interrupt-present = <0x0>;
xlnx,is-dual = <0x0>;
xlnx,tri-default = <0xFFFFFFFF>;
xlnx,tri-default-2 = <0xFFFFFFFF>;
};
PMOD_2: gpio@80030000 {
#gpio-cells = <2>;
clock-names = "s_axi_aclk";
clocks = <&zynqmp_clk 71>;
compatible = "xlnx,axi-gpio-2.0", "xlnx,xps-gpio-1.00.a";
gpio-controller ;
reg = <0x0 0x80030000 0x0 0x10000>;
xlnx,all-inputs = <0x0>;
xlnx,all-inputs-2 = <0x0>;
xlnx,all-outputs = <0x0>;
xlnx,all-outputs-2 = <0x0>;
xlnx,dout-default = <0x00000000>;
xlnx,dout-default-2 = <0x00000000>;
xlnx,gpio-width = <0x8>;
xlnx,gpio2-width = <0x20>;
xlnx,interrupt-present = <0x0>;
xlnx,is-dual = <0x0>;
xlnx,tri-default = <0xFFFFFFFF>;
xlnx,tri-default-2 = <0xFFFFFFFF>;
};
PMOD_3: gpio@80040000 {
#gpio-cells = <2>;
clock-names = "s_axi_aclk";
clocks = <&zynqmp_clk 71>;
compatible = "xlnx,axi-gpio-2.0", "xlnx,xps-gpio-1.00.a";
gpio-controller ;
reg = <0x0 0x80040000 0x0 0x10000>;
xlnx,all-inputs = <0x0>;
xlnx,all-inputs-2 = <0x0>;
xlnx,all-outputs = <0x0>;
xlnx,all-outputs-2 = <0x0>;
xlnx,dout-default = <0x00000000>;
xlnx,dout-default-2 = <0x00000000>;
xlnx,gpio-width = <0x8>;
xlnx,gpio2-width = <0x20>;
xlnx,interrupt-present = <0x0>;
xlnx,is-dual = <0x0>;
xlnx,tri-default = <0xFFFFFFFF>;
xlnx,tri-default-2 = <0xFFFFFFFF>;
};
axi_dma_0: dma@80050000 {
#dma-cells = <1>;
clock-names = "s_axi_lite_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk";
clocks = <&zynqmp_clk 71>, <&zynqmp_clk 71>, <&zynqmp_clk 71>;
compatible = "generic-uio";
reg = <0x0 0x80050000 0x0 0x10000>;
xlnx,addrwidth = <0x20>;
xlnx,sg-length-width = <0xe>;
dma-channel@80050000 {
compatible = "xlnx,axi-dma-mm2s-channel";
dma-channels = <0x1>;
xlnx,datawidth = <0x20>;
xlnx,device-id = <0x0>;
};
dma-channel@80050030 {
compatible = "xlnx,axi-dma-s2mm-channel";
dma-channels = <0x1>;
xlnx,datawidth = <0x20>;
xlnx,device-id = <0x0>;
};
};
axi_intc_0: interrupt-controller@80000000 {
#interrupt-cells = <2>;
clock-names = "s_axi_aclk";
clocks = <&zynqmp_clk 71>;
compatible = "generic-uio";
interrupt-controller ;
interrupt-names = "irq";
interrupt-parent = <&gic>;
interrupts = <0 89 4>;
reg = <0x0 0x80000000 0x0 0x10000>;
xlnx,kind-of-intr = <0xfffffffd>;
xlnx,num-intr-inputs = <0x20>;
};
axi_timer_0: timer@80060000 {
clock-frequency = <99999001>;
clock-names = "s_axi_aclk";
clocks = <&zynqmp_clk 71>;
compatible = "generic-uio";
reg = <0x0 0x80060000 0x0 0x10000>;
xlnx,count-width = <0x20>;
xlnx,gen0-assert = <0x1>;
xlnx,gen1-assert = <0x1>;
xlnx,one-timer-only = <0x0>;
xlnx,trig0-assert = <0x1>;
xlnx,trig1-assert = <0x1>;
};
krnl_vadd_1: krnl_vadd@b0000000 {
/* This is a place holder node for a custom IP, user may need to update the entries */
clock-names = "ap_clk";
clocks = <&misc_clk_0>;
compatible = "generic-uio";
interrupt-names = "interrupt";
interrupt-parent = <&axi_intc_0>;
interrupts = <1 2>;
reg = <0x0 0xb0000000 0x0 0x10000>;
xlnx,s-axi-control-addr-width = <0x6>;
xlnx,s-axi-control-data-width = <0x20>;
};
misc_clk_0: misc_clk_0 {
#clock-cells = <0>;
clock-frequency = <199998000>;
compatible = "fixed-clock";
};
multi_axi4ls_0: multi_axi4ls@80080000 {
/* This is a place holder node for a custom IP, user may need to update the entries */
clock-names = "ap_clk";
clocks = <&zynqmp_clk 71>;
compatible = "generic-uio";
reg = <0x0 0x80080000 0x0 0x10000>;
xlnx,s-axi-control-addr-width = <0x6>;
xlnx,s-axi-control-data-width = <0x20>;
};
zyxclmm_drm {
compatible = "xlnx,zocl";
interrupts-extended = <&axi_intc_0 0 4>, <&axi_intc_0 1 4>, <&axi_intc_0 2 4>, <&axi_intc_0 3 4>, <&axi_intc_0 4 4>, <&axi_intc_0 5 4>, <&axi_intc_0 6 4>, <&axi_intc_0 7 4>, <&axi_intc_0 8 4>, <&axi_intc_0 9 4>,
<&axi_intc_0 10 4>, <&axi_intc_0 11 4>, <&axi_intc_0 12 4>, <&axi_intc_0 13 4>, <&axi_intc_0 14 4>,
<&axi_intc_0 15 4>, <&axi_intc_0 16 4>, <&axi_intc_0 17 4>, <&axi_intc_0 18 4>, <&axi_intc_0 19 4>,
<&axi_intc_0 20 4>, <&axi_intc_0 21 4>, <&axi_intc_0 22 4>, <&axi_intc_0 23 4>, <&axi_intc_0 24 4>,
<&axi_intc_0 25 4>, <&axi_intc_0 26 4>, <&axi_intc_0 27 4>, <&axi_intc_0 28 4>, <&axi_intc_0 29 4>,
<&axi_intc_0 30 4>, <&axi_intc_0 31 4 >;
};
};
};
};
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|---|---|---|---|---|---|---|
| - | - | - | - | 1 | 2 | 3 |
| 4 | 5 | 6 | 7 | 8 | 9 | 10 |
| 11 | 12 | 13 | 14 | 15 | 16 | 17 |
| 18 | 19 | 20 | 21 | 22 | 23 | 24 |
| 25 | 26 | 27 | 28 | 29 | 30 | - |