output reg [4*DDR2_DQS_DM_WIDTH-1 : 0] dqs_oserdes_d_1d;
output reg [4*DDR2_DQS_DM_WIDTH-1 : 0] dqs_oserdes_t_1d;
always @(posedge clk) begin : DQS_OSERDES_1D // dqs_oserdes_d_1dとdqs_oserdes_t_1dがOSERDESに入力される
integer k;
for(k=0; k<=DDR2_DQS_DM_WIDTH-1; k=k+1) begin // 8bitに1個インスタンシエーション
if (reset) begin
dqs_oserdes_d_1d[k*4+3 : k*4] <= 4'bXXXX;
dqs_oserdes_t_1d[k*4+3 : k*4] <= 4'b1111;
end else begin
dqs_oserdes_d_1d[k*4+3 : k*4] <= dqs_oserdes_d;
dqs_oserdes_t_1d[k*4+3 : k*4] <= dqs_oserdes_t;
end
end
end
always @(posedge clk) begin : DQS_OSERDES_1D // dqs_oserdes_d_1dとdqs_oserdes_t_1dがOSERDESに入力される
integer k, m;
for(k=0; k<=DDR2_DQS_DM_WIDTH-1; k=k+1) begin // 8bitに1個インスタンシエーション
for(m=0; m<4; m=m+1) begin
if (reset) begin
dqs_oserdes_d_1d[k*4+m] <= 1'bX;
dqs_oserdes_t_1d[k*4+m] <= 1'b1;
end else begin
dqs_oserdes_d_1d[k*4+m] <= dqs_oserdes_d[m];
dqs_oserdes_t_1d[k*4+m] <= dqs_oserdes_t[m];
end
end
end
end
always @(posedge clk) begin : DQS_OSERDES_1D // dqs_oserdes_d_1dとdqs_oserdes_t_1dがOSERDESに入力される
integer k, m;
for(k=0; k<=DDR2_DQS_DM_WIDTH-1; k=k+1) begin // 8bitに1個インスタンシエーション
if (reset) begin
dqs_oserdes_d_1d[k*4 +: 4] <= 4'bXXXX;
dqs_oserdes_t_1d[k*4 +: 4] <= 4'b1111;
end else begin
dqs_oserdes_d_1d[k*4 +: 4] <= dqs_oserdes_d;
dqs_oserdes_t_1d[k*4 +: 4] <= dqs_oserdes_t;
end
end
end
reg [8:0] a;
のとき、
a[1 +:4] は、a[4:1] に等価です。1から出発して1,2,3,4 のパートセレクト
a[5 -:4: は、a[5:2] に等価です。5から出発して5,4,3,2のパートセレクト
generate
genvar k, m;
for(k=0; k<=DDR2_DQS_DM_WIDTH-1; k=k+1) begin : OSERDES_NO // 8bitに1個インスタンシエーション
for(m=0; m<4; m=m+1) begin : OSERDES_PIN_NO
always @(posedge clk) begin
if (reset) begin
dqs_oserdes_d_1d[k*4+m] <= 1'bX;
dqs_oserdes_t_1d[k*4+m] <= 1'b1;
end else begin
dqs_oserdes_d_1d[k*4+m] <= dqs_oserdes_d[m];
dqs_oserdes_t_1d[k*4+m] <= dqs_oserdes_t[m];
end
end
end
end
endgenerate
assign fifo_full = (rp-1==wp) ? 1'b1: 1'b0;
assign fifo_full = (rp-4'h1==wp) ? 1'b1: 1'b0;
`timescale 1ps/1ps
...........
initial begin // 10bitを出力
#100000; // GSRリセットを待つ
#(PERIOD*2);
rst = 1'b0;
endmodule
`default_nettype wire
// ps2read Verilog2001
`default_nettype none
`timescale 1ns / 1ps
module ps2read(clk, reset, ps2clk, ps2data, scandata);
input clk, reset, ps2clk, ps2data;
output [7:0] scandata;
wire clk, reset, ps2clk, ps2data;
reg [7:0] scandata;
reg [10:0] c_state, n_state;
reg ps2clk_b1, ps2clk_b2;
reg ps2data_b;
reg [7:0] c_scandata, n_scandata;
parameter IDLE=11'b00000000001, BIT0=11'b00000000010, BIT1=11'b00000000100, BIT2=11'b00000001000, BIT3=11'b00000010000, BIT4=11'b00000100000, BIT5=11'b00001000000, BIT6=11'b00010000000, BIT7=11'b00100000000, PARITY=11'b01000000000, STOP=11'b10000000000;
always @(posedge reset, posedge clk) begin
if (reset) begin
ps2clk_b1 <= 1'b0;
ps2clk_b2 <= 1'b0;
ps2data_b <= 1'b0;
end else begin
ps2clk_b1 <= ps2clk;
ps2clk_b2 <= ps2clk_b1;
ps2data_b <= ps2data;
end
end
always @(posedge reset, posedge clk) begin
if (reset) begin
c_state <= IDLE;
c_scandata <= 0;
end else begin
c_state <= n_state;
c_scandata <= n_scandata;
end
end
always @* begin
case (c_state)
IDLE : begin
n_scandata <= c_scandata;
if (ps2clk_b2 && !ps2clk_b1)
n_state <= BIT0;
else
n_state <= IDLE;
end
BIT0 :
if (ps2clk_b2 && !ps2clk_b1) begin
n_state <= BIT1;
n_scandata <= {ps2data_b, c_scandata[7:1]};
end else begin
n_state <= BIT0;
n_scandata <= c_scandata;
end
BIT1 :
if (ps2clk_b2 && !ps2clk_b1) begin
n_state <= BIT2;
n_scandata <= {ps2data_b, c_scandata[7:1]};
end else begin
n_state <= BIT1;
n_scandata <= c_scandata;
end
BIT2 :
if (ps2clk_b2 && !ps2clk_b1) begin
n_state <= BIT3;
n_scandata <= {ps2data_b, c_scandata[7:1]};
end else begin
n_state <= BIT2;
n_scandata <= c_scandata;
end
BIT3 :
if (ps2clk_b2 && !ps2clk_b1) begin
n_state <= BIT4;
n_scandata <= {ps2data_b, c_scandata[7:1]};
end else begin
n_state <= BIT3;
n_scandata <= c_scandata;
end
BIT4 :
if (ps2clk_b2 && !ps2clk_b1) begin
n_state <= BIT5;
n_scandata <= {ps2data_b, c_scandata[7:1]};
end else begin
n_state <= BIT4;
n_scandata <= c_scandata;
end
BIT5 :
if (ps2clk_b2 && !ps2clk_b1) begin
n_state <= BIT6;
n_scandata <= {ps2data_b, c_scandata[7:1]};
end else begin
n_state <= BIT5;
n_scandata <= c_scandata;
end
BIT6 :
if (ps2clk_b2 && !ps2clk_b1) begin
n_state <= BIT7;
n_scandata <= {ps2data_b, c_scandata[7:1]};
end else begin
n_state <= BIT6;
n_scandata <= c_scandata;
end
BIT7 :
if (ps2clk_b2 && !ps2clk_b1) begin
n_state <= PARITY;
n_scandata <= {ps2data_b, c_scandata[7:1]};
end else begin
n_state <= BIT7;
n_scandata <= c_scandata;
end
PARITY : begin
n_scandata <= c_scandata;
if (ps2clk_b2 && !ps2clk_b1)
n_state <= STOP;
else
n_state <= PARITY;
end
STOP : begin
n_scandata <= c_scandata;
if (ps2clk_b2 && !ps2clk_b1)
n_state <= IDLE;
else
n_state <= STOP;
end
endcase
end
always @(posedge reset, posedge clk) begin
if (reset)
scandata <= 0;
else
if (c_state == STOP)
scandata <= c_scandata;
end
// synthesis translate_off
reg [20*8:1] MAIN_STATE;
always @(c_state) begin
case(c_state)
IDLE: MAIN_STATE <= "IDLE";
BIT0: MAIN_STATE <= "BIT0";
BIT1: MAIN_STATE <= "BIT1";
BIT2: MAIN_STATE <= "BIT2";
BIT3: MAIN_STATE <= "BIT3";
BIT4: MAIN_STATE <= "BIT4";
BIT5: MAIN_STATE <= "BIT5";
BIT6: MAIN_STATE <= "BIT6";
BIT7: MAIN_STATE <= "BIT7";
PARITY: MAIN_STATE <= "PARITY";
STOP: MAIN_STATE <= "STOP";
endcase
end
// synthesis translate_on
endmodule
`default_nettype none
`timescale 1ns / 1ps
module ps2read_tb;
parameter CYCLE=20;
reg clk, reset, ps2clk, ps2data;
wire [7:0] scandata;
ps2read ps2read_inst (
.clk(clk),
.reset(reset),
.ps2clk(ps2clk),
.ps2data(ps2data),
.scandata(scandata)
);
initial begin
clk <= 1'b1;
end
always #(CYCLE/2)
clk <= ~clk;
initial begin
reset <= 1'b1;
ps2clk <= 1'b1;
ps2data <= 1'b1;
#80; // リセット
reset <= 1'b0; // リセット解除
PS2_SigGen(8'h1C);
PS2_SigGen(8'h32);
#500;
$stop;
end
task PS2_SigGen;
input [7:0] input_code;
integer i;
begin
ps2clk <= 1'b1;
ps2data <= 1'b0; // Stop bit
#40000;
ps2clk <= 1'b0; // 立ち下がりエッジ
#40000;
for(i=0; i<=7; i=i+1) begin
ps2clk <= 1'b1; // 立ち上がりエッジ
ps2data <= input_code[i]; // シリアルデータ出力
#40000;
ps2clk <= 1'b0; // 立下りエッジ
#40000;
end
ps2clk <= 1'b1;
ps2data <= !(^input_code);
#40000;
ps2clk <= 1'b0; // 立ち下がりエッジ
#40000;
ps2clk <= 1'b1;
ps2data <= 1'b1; // Stop bit
#40000;
ps2clk <= 1'b0; // 立ち下がりエッジ
#40000;
ps2clk <= 1'b1; // 1に戻す
end
endtask
endmodule
(* IOSTANDARD="LVDCI_33" *) input rxd ;
(* KEEP="TURE" *) wire fifo_full;
日 | 月 | 火 | 水 | 木 | 金 | 土 |
---|---|---|---|---|---|---|
- | - | - | - | - | 1 | 2 |
3 | 4 | 5 | 6 | 7 | 8 | 9 |
10 | 11 | 12 | 13 | 14 | 15 | 16 |
17 | 18 | 19 | 20 | 21 | 22 | 23 |
24 | 25 | 26 | 27 | 28 | 29 | 30 |
31 | - | - | - | - | - | - |